Simon L Johnson

US Patent:

6449523, Sep 10, 2002

Filed:

Oct 15, 1999

Appl. No.:

09/419172

Inventors:

Bradley Morris Johnson - Edmonds WA
Lev M. Bolotin - Kirkland WA
Simon B. Johnson - Kirkland WA
Carl W. Olson - Renton WA
Bryan D. Powell - Maple Valley WA

Assignee:

Data I/O Corporation - Redmond WA

International Classification:

G06F 1900

US Classification:

700121, 700219

Abstract:

A feeder/programming/buffer operating system is provided which controls a feeder mechanism, a programming mechanism, an electronic handling mechanism, a pneumatic handling mechanism, and a plurality of sensors. The operating system programs programmable devices and makes the feeder/programming/buffer system substantially independent of a production assembly system with which it is capable of being integrated yet fully responsive to the requirements of the production assembly system.

US Patent:

20070276965, Nov 29, 2007

Filed:

May 4, 2006

Appl. No.:

11/381696

Inventors:

Bradley Johnson - Edmonds WA, US
Lev Bolotin - Kirkland WA, US
Simon Johnson - Bonney Lake WA, US

Assignee:

DATA I/O CORPORATION - Redmond WA

International Classification:

G06F 3/00

US Classification:

710008000

Abstract:

An automated programming system that includes providing a smart interface system for recognizing an intelligent module installed within the automated programming system. Configuring the intelligent module with a composite connection for transmitting information between the intelligent module and the smart interface system, and linking the intelligent module to the smart interface system for communicating information.

US Patent:

50035070, Mar 26, 1991

Filed:

Sep 6, 1988

Appl. No.:

7/241385

Inventors:

Simon Johnson - Woodinville WA

International Classification:

G11C 700
G11C 2900

US Classification:

364900

Abstract:

An EPROM emulator makes use of a simple device with a housing connected to a eprom header which serves to connect the device to a circuit board in conjunction with a microprocessor emulator. Inside the housing are paging and data select circuits and a set of SRAM which are used in place of a traditional EPROM to hold the programming information. To program the device, the EPROM simulator is connected to the circuit board in place of an eprom. A switch on the housing is then turned to place the device in programming mode. The same switch also determines how the device is programmed by accessing the appropriate data lines for the number of pages of EPROM memory which are being emulated. After the switch is properly selected, the emulator is programmed by sending the data through the eprom socket on the circuit board via the microprocessor emulator. After the device is programmed, the switch on the housing is turned to place the device in read-only mode so that it can simulate an EPROM.

US Patent:

20210117350, Apr 22, 2021

Filed:

Dec 25, 2020

Appl. No.:

17/134242

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
H04L 12/933
G06F 12/0813
G06F 12/0815
G06F 12/0831
G06F 13/42
G06F 8/71
G06F 8/77
G06F 9/30
G06F 12/0806
G06F 9/46
G06F 13/40
G06F 9/445
G06F 1/3287
G06F 11/10
H04L 9/06
G06F 12/0808

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

US Patent:

20200356502, Nov 12, 2020

Filed:

Jul 23, 2020

Appl. No.:

16/937499

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
H04L 12/933
G06F 12/0813
G06F 12/0815
G06F 12/0831
G06F 13/42
G06F 8/71
G06F 8/77
G06F 9/30
G06F 12/0806
G06F 9/46
G06F 13/40
G06F 9/445
G06F 1/3287
G06F 11/10
H04L 9/06
G06F 12/0808

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

US Patent:

20190391939, Dec 26, 2019

Filed:

Feb 25, 2019

Appl. No.:

16/285035

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
G06F 12/0808
H04L 9/06
G06F 13/42
G06F 11/10
G06F 13/40
G06F 1/3287
G06F 9/445
G06F 9/46
G06F 12/0831
G06F 12/0806
G06F 9/30
G06F 8/77
G06F 8/71
G06F 12/0815
G06F 12/0813
H04L 12/933

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

US Patent:

20170109315, Apr 20, 2017

Filed:

Dec 28, 2016

Appl. No.:

15/393153

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Round Rock TX, US
Jeff Willey - Timnath CO, US
Robert H. Beers - Beaverton OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Brookline MA, US
Debendra Das Sharma - Saratoga, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/42
H04L 9/06
G06F 11/10
G06F 13/40

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.