Simon Wood

Address:

3339 Sugar House St, Raleigh, NC 27614

Phone:

9194358339

VIN:

2C4GM68425R659885

Make:

CHRYSLER

Model:

PACIFICA

Year:

2007

US Patent:

8076994, Dec 13, 2011

Filed:

Jun 22, 2007

Appl. No.:

11/767161

Inventors:

Donald Farrell - Raleigh NC, US
Simon Wood - Raleigh NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H03H 7/38

US Classification:

333 32, 330302

Abstract:

A packaged RE power device includes a transistor having a control terminal and an output terminal and configured to operate at a fundamental operating frequency, an RF signal input lead coupled to the control terminal, and an RF signal output lead coupled to the output terminal. A harmonic reducer is coupled to the control terminal and/or the output terminal of the transistor and is configured to provide a short circuit or low impedance path from the control terminal and/or the output terminal to ground for signals at an Nth harmonic frequency of the fundamental operating frequency, where N>1. The device further includes a package that houses the transistor and the harmonic reducer, with the input lead and the output lead extending from the package. Multi-chip packages are also disclosed.

US Patent:

8330265, Dec 11, 2012

Filed:

Jun 22, 2007

Appl. No.:

11/767172

Inventors:

Donald Farrell - Raleigh NC, US
Simon Wood - Raleigh NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 23/48

US Classification:

257690, 257691, 438106, 333 32

Abstract:

A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells.

US Patent:

8592966, Nov 26, 2013

Filed:

Dec 8, 2010

Appl. No.:

12/962923

Inventors:

Simon Wood - Raleigh NC, US
Bradley Millon - Durham NC, US

Assignee:

Cree, Inc. - Durham NC

International Classification:

H01L 23/48

US Classification:

257690, 257691, 438106, 333 32

Abstract:

A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells. The input matching network further includes a plurality of resistors coupled respectively between adjacent input terminals of the capacitors.

US Patent:

20130015924, Jan 17, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/537933

Inventors:

Ulf Hakan Andre - Hillsborough NC, US
Simon Maurice Wood - Raleigh NC, US

International Classification:

H03H 7/38

US Classification:

333 32

Abstract:

A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells, an RF input lead coupled to the plurality of RF transistor cells, an RF output lead, and an output matching network coupled between the plurality of RF transistor cells and the RF output lead. The output matching network includes a plurality of capacitors having respective upper capacitor plates, wherein the upper capacitor plates of the capacitors are coupled to output terminals of respective ones of the RF transistor cells. The plurality of capacitors may be provided as a capacitor block that includes a common reference capacitor plate and a dielectric layer on the reference capacitor plate. The upper capacitor plates may be on the dielectric layer.

US Patent:

20200321458, Oct 8, 2020

Filed:

Jun 22, 2020

Appl. No.:

16/907983

Inventors:

- Durham NC, US
Simon Wood - Raleigh NC, US

International Classification:

H01L 29/778
H01L 29/417
H01L 29/423
H01L 23/522
H01L 23/528
H01L 29/06
H01L 29/20
H01L 29/205

Abstract:

A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

US Patent:

20190102498, Apr 4, 2019

Filed:

Oct 3, 2017

Appl. No.:

15/723286

Inventors:

- Durham NC, US
Ulf Andre - Hillsborough NC, US
Khaled Fayed - Cary NC, US
Simon Wood - Raleigh NC, US

International Classification:

G06F 17/50
H01L 27/02
H01L 27/088
H01L 23/66
H01L 23/00
H01L 29/778
H03F 3/213
H03F 3/195
H03F 1/56

Abstract:

A packaged transistor amplifier includes a package having an input lead and an output lead; a transistor stage having a plurality of unit cell transistors that are electrically coupled to the input lead in parallel, each of the unit cell transistors having an output; a first output bond pad that is coupled to a first subset of the outputs of the unit cell transistors by a first feed network; a second output bond pad that is separate from the first output bond pad, the second output bond pad coupled to a second subset of the outputs of the unit cell transistors by a second feed network; a first output bond wire coupled between the first output bond pad and the output lead; and a second output bond wire coupled between the second output bond pad and the output lead. Related design methods are also provided.

US Patent:

20190088772, Mar 21, 2019

Filed:

Nov 7, 2018

Appl. No.:

16/182642

Inventors:

- Durham NC, US
Simon Wood - Raleigh NC, US

International Classification:

H01L 29/778
H01L 29/06
H01L 29/205
H01L 29/417
H01L 29/20
H01L 23/522
H01L 23/528
H01L 29/423

Abstract:

A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

US Patent:

20170271329, Sep 21, 2017

Filed:

Mar 17, 2016

Appl. No.:

15/073201

Inventors:

- Durham NC, US
Simon Wood - Raleigh NC, US
Scott Sheppard - Chapel Hill NC, US
Dan Namishia - Wake Forest NC, US

International Classification:

H01L 27/088
H01L 29/423
H01L 29/417
H01L 29/40

Abstract:

A transistor device includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent the source contact, and a drain contact adjacent the gate finger, wherein the gate finger is between the drain contact and the source contact. The device further includes a gate jumper extending in the first direction, a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar that is spaced apart from the gate bus in the first direction and that connects the gate jumper to the gate finger.