Smeeta Jain Gupta

US Patent:

50580485, Oct 15, 1991

Filed:

Apr 2, 1990

Appl. No.:

7/503819

Inventors:

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

364748

Abstract:

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

US Patent:

49263234, May 15, 1990

Filed:

Mar 3, 1988

Appl. No.:

7/163917

Inventors:

Gigy Baror - Austin TX
Brian W. Case - Sunnyvale CA
Rod G. Fleck - Munich, DE
Philip M. Freidin - Sunnyvale CA
Smeeta Gupta - Saratoga CA
William M. Johnson - San Jose CA
Cheng-Gang Kong - Saratoga CA
Ole H. Moller - Lyngby, DK
Timothy A. Olson - Sunnyvale CA
David I. Sorensen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 940
G06F 900

US Classification:

364200

Abstract:

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program. In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles.

US Patent:

52671860, Nov 30, 1993

Filed:

Jul 23, 1991

Appl. No.:

7/734762

Inventors:

Smeeta Gupta - Saratoga CA
Robert M. Perlman - San Jose CA
Thomas W. Lynch - Austin TX
Brian D. McMinn - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

364748

Abstract:

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.