Srenik S Mehta

US Patent:

6928127, Aug 9, 2005

Filed:

Mar 11, 2003

Appl. No.:

10/387231

Inventors:

Michael P. Mack - Sunnyvale CA, US
Srenik Mehta - San Francisco CA, US

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H04L007/00

US Classification:

375371

Abstract:

A frequency synthesizer and a method for frequency synthesis are disclosed. The frequency synthesizer comprises a voltage controlled oscillator for generating an output signal having a synthesized frequency, and a prescaler connected to the VCO for receiving the output signal and providing a feedback signal. The prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal.

US Patent:

7051063, May 23, 2006

Filed:

May 3, 2002

Appl. No.:

10/138848

Inventors:

Brian Kaczynski - Los Altos CA, US
Srenik Mehta - Pleasanton CA, US

Assignee:

Atheros Communications, Inc. - Santa Clara CA

International Classification:

G06G 7/02

US Classification:

708819, 708 5

Abstract:

A channel select filter circuit is disclosed using a current-mode transconductance-capacitor (gm-C) architecture, which is tuned by digitally controlled capacitor arrays. The main filter includes at least one transconductor-capacitor (gm-C) filter and a transresistance amplifier. A replica transconductor-capacitor (gm-C) filter and a phase detector are used to establish any phase shift in an input signal, and a state machine adjusts capacitor arrays in the the replica transconductor-capacitor (gm-C) filter and the at least one transconductor-capacitor (gm-C) filter in order to set a cut-off frequency of the channel select filter.

US Patent:

7065327, Jun 20, 2006

Filed:

Sep 10, 1999

Appl. No.:

09/762720

Inventors:

Donald Evan Macnally - San Francisco CA, US
Thomas B. Cho - Alameda CA, US
Shahriar Rabii - Palo Alto CA, US
Srenik Suresh Mehta - Pleasanton CA, US
Christopher Donald Nilson - San Jose CA, US
Michael Peter Mack - San Francisco CA, US
Laurence Marguerite Plouvier - San Francisco CA, US
Menno Marringa - San Francisco CA, US
Eric S. Dukatz - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/44

US Classification:

455 78, 455 83

Abstract:

A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

US Patent:

7132865, Nov 7, 2006

Filed:

Jul 23, 2004

Appl. No.:

10/898423

Inventors:

Manolis Terrovitis - Berkeley CA, US
Srenik Mehta - Pleasanton CA, US

Assignee:

Atheros Communications, Inc. - Santa Clara CA

International Classification:

H03L 7/06

US Classification:

327157, 331 16

Abstract:

Parasitic current at the control voltage node of a phase-locked loop (PLL) can significantly reduce performance of the PLL. Off-state transistors in either the charge pump or the filter can cause this parasitic current. A method of canceling a parasitic current generated by the charge pump in the PLL is described. In this method, a leakage current associated with leaky circuits in the charge pump can be determined. An opposing current can be injected to the control voltage node. This opposing current is equal, but opposite, to the leakage current. A method of eliminating a parasitic current generated by the filter in the PLL is also described. In this method, for each programmable capacitor in an unused state, a unity gain buffer can charge the capacitor to the same potential as the control voltage node, thereby providing the same potential on both sides of the switch.

US Patent:

8106715, Jan 31, 2012

Filed:

Dec 4, 2009

Appl. No.:

12/630916

Inventors:

Bita Nezamfar - Mountain View CA, US
Srenik Mehta - Union City CA, US

Assignee:

Qualcomm Atheros, Inc. - San Jose CA

International Classification:

H03K 3/03
H03L 1/02

US Classification:

331 46, 331143, 331176

Abstract:

In order to decrease the temperature sensitivity of an oscillator output, and obtain a frequency of oscillation that remains stable over variations in temperature, two oscillators may be configured with identical comparators and logic circuitry, but having different oscillation frequencies. The different oscillation frequencies may be achieved by configuring each oscillator with a respective resistor divider circuit configured to adjust the reference voltage at the reference input of the respective comparator. The difference between the respective periods of oscillation of the two oscillators may therefore become independent of the comparator delay, and may only depend on temperature sensitivity of the resistor. The output of one oscillator may be used to calibrate/adjust the output of the other oscillator based on the difference between the respective periods of oscillation of the two oscillators, due to the difference between the respective periods of oscillation of the two oscillators remaining substantially independent of variations in temperature.

US Patent:

8155612, Apr 10, 2012

Filed:

Nov 25, 2008

Appl. No.:

12/323338

Inventors:

Paul J. Husted - San Jose CA, US
Srenik Mehta - Union City CA, US
Soner Ozgur - Santa Clara CA, US

Assignee:

Qualcomm Atheros, Inc. - San Jose CA

International Classification:

H04B 1/06

US Classification:

4552341, 455 84, 455132, 4552321, 4552342

Abstract:

A wireless device that can process signals according to multiple wireless protocols simultaneously and without signal loss. The wireless device may comprise an antenna and first and second wireless protocol circuitry. The first wireless protocol circuitry comprises a shared gain element that amplifies signals that are processed by each of the first and second wireless protocol circuitry. Since the third signals are amplified by the shared gain element prior to being split out to the respective protocol circuitry, the first and second portions of the amplified third signals do not have significant signal loss relative to the third signals provided by the antenna. Thus the wireless device can receive and process wireless signals according to both the first and second protocols simultaneously without any significant signal losses due to splitting of the receive signal.

US Patent:

8204451, Jun 19, 2012

Filed:

Jul 30, 2008

Appl. No.:

12/182232

Inventors:

Alireza Kheirkhahi - Irvine CA, US
Hirad Samavati - Santa Clara CA, US
Srenik Mehta - Union City CA, US
David Su - Santa Clara CA, US
Brian Kaczynski - Krakow, PL

Assignee:

QUALCOMM Atheros, Inc. - San Jose CA

International Classification:

H04B 1/40

US Classification:

455 84, 455 83, 455 82, 370280

Abstract:

A transceiver for use in a wireless device. The transceiver may include a receive portion for receiving an input RF signal. The receive portion may include at least one receive filter which may include a first filter. The transceiver may also include a transmit portion for transmitting an output RF signal. The transmit portion may include at least one transmit filter, which may include the first filter used in the receive portion. The transceiver may further include a plurality of switches, which may include a first switch coupled to an input of the first filter and a second switch coupled to an output of the first filter. The plurality of switches may be configurable to enable use of the first filter in the receive portion for receiving the input RF signal and use of the first filter in the transmit portion for transmitting the output RF signal.

US Patent:

8488506, Jul 16, 2013

Filed:

Jun 28, 2011

Appl. No.:

13/171275

Inventors:

Paul J. Husted - San Jose CA, US
Srenik Mehta - Union City CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G08C 17/00

US Classification:

370311, 455574

Abstract:

Techniques are disclosed relating to oscillator settling time allowance. In one embodiment, an apparatus may include an oscillator and oscillation detection and control circuitry. The oscillation detection and control circuitry may be configured to awaken an oscillator at a predetermined time and detect an edge transition of oscillations. The oscillation detection and control circuitry may further be configured to measure the time from the power-on indication to edge transition detection. In one embodiment, the oscillation detection and control circuitry may be configured to store the measured time and use the measured time instead of the predetermined time for subsequent oscillator awakenings. In some embodiments, the apparatus may further include circuitry configured to compensate for an expected oscillator settling behavior.