Sridhar P Lakshmanamurthy

US Patent:

6906980, Jun 14, 2005

Filed:

Jan 8, 2003

Appl. No.:

10/338429

Inventors:

Chen-Chi Kuo - Pleasanton CA, US
Senthil Nathan Arunachalam - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Uday Naik - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C008/00

US Classification:

36523003, 710 52, 710 56

Abstract:

According to some embodiments, an arrangement of buffers in memory banks is provided.

US Patent:

7103821, Sep 5, 2006

Filed:

Jul 3, 2002

Appl. No.:

10/188516

Inventors:

Sridhar Lakshmanamurthy - Sunnyvale CA, US
Charles E. Narad - Los Altos CA, US
Lawrence B. Huston - Wexford PA, US
Yim Pun - Saratoga CA, US
Kin-Yip Liu - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714758

Abstract:

A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.

US Patent:

7158438, Jan 2, 2007

Filed:

Mar 29, 2005

Appl. No.:

11/092010

Inventors:

Chen-Chi Kuo - Pleasanton CA, US
Senthil Nathan Arunachalam - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Uday Naik - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 8/00

US Classification:

36523003, 710 52, 710 56

Abstract:

An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

US Patent:

7185153, Feb 27, 2007

Filed:

Dec 18, 2003

Appl. No.:

10/742189

Inventors:

Prashant R. Chandra - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Chen-Chi Kuo - Pleasanton CA, US
Rohit Natarajan - Sunnyvale CA, US
Mark Rosenbluth - Uxbridge MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711155, 711100, 711154, 711170

Abstract:

In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

US Patent:

7200699, Apr 3, 2007

Filed:

Sep 2, 2004

Appl. No.:

10/933621

Inventors:

Bijoy Bose - San Jose CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Mark B. Rosenbluth - Uxbridge MA, US
Irwin Vaz - San Jose CA, US
Alok Mathur - Milpitas CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/368

US Classification:

710120, 710317

Abstract:

A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers.

US Patent:

7210008, Apr 24, 2007

Filed:

Dec 18, 2003

Appl. No.:

10/741298

Inventors:

Prashant R. Chandra - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Chen-Chi Kuo - Pleasanton CA, US
Rohit Natarajan - Sunnyvale CA, US
Mark Rosenbluth - Uxbridge MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711154, 711202, 710 66

Abstract:

A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

US Patent:

7213099, May 1, 2007

Filed:

Dec 30, 2003

Appl. No.:

10/751263

Inventors:

Chen-Chi Kuo - Pleasanton CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Rohit Natarajan - Sunnyvale CA, US
Kin-Yip Liu - San Jose CA, US
Prashant R. Chandra - Sunnyvale CA, US
James D. Guilford - Northborough MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/06

US Classification:

711 5

Abstract:

Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

US Patent:

7251219, Jul 31, 2007

Filed:

Jul 3, 2002

Appl. No.:

10/188081

Inventors:

Sridhar Lakshmanamurthy - Sunnyvale CA, US
Lawrence B. Huston - Wexford PA, US
Yim Pun - Saratoga CA, US
Raymond Ng - Fremont CA, US
Mark B. Rosenbluth - Uxbridge MA, US
David Romano - Cumberland RI, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/44

US Classification:

370236, 370413

Abstract:

In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.