Sridhar K Seshadri

US Patent:

8341570, Dec 25, 2012

Filed:

Jan 26, 2012

Appl. No.:

13/359386

Inventors:

Manish Jain - San Jose CA, US
Subha S. Chowdhury - West Bengal, IN
Sridhar Seshadri - Sunnyvale CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716106, 703 14

Abstract:

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

US Patent:

20090276738, Nov 5, 2009

Filed:

Apr 30, 2008

Appl. No.:

12/112222

Inventors:

Manish Jain - San Jose CA, US
Subha S. Chowdhury - Kolkata, IN
Sridhar Seshadri - Sunnyvale CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 9/45

US Classification:

716 5

Abstract:

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

US Patent:

20130085738, Apr 4, 2013

Filed:

Nov 26, 2012

Appl. No.:

13/685412

Inventors:

Subha S. Chowdhury - Kolkata, IN
Sridhar Seshadri - Sunnyvale CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

US Patent:

20140244233, Aug 28, 2014

Filed:

May 8, 2014

Appl. No.:

14/273152

Inventors:

- Mountain View CA, US
Subha S. Chowdhury - Kolkata, IN
Sridhar Seshadri - Sunnyvale CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.