Sriram Satakopan

US Patent:

7032200, Apr 18, 2006

Filed:

Sep 9, 2003

Appl. No.:

10/657964

Inventors:

Sriram Satakopan - Sunnyvale CA, US
Arvindvel Shanmugavel - Mountain View CA, US
Shunjiang Xu - Sunnyvale CA, US
Von-Kyoung Kim - Santa Clara CA, US
Peter Lai - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 4, 716 5

Abstract:

A technique improves the performance of an integrated circuit design by selectively replacing low Vtransistors with standard Vtransistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vvariant of a gate instance increases a path cycle time as compared to a standard Vcounterpart, the maximum of the path cycle times for all paths that include the low Vvariant and the maximum of the path cycle time for these paths with a standard Vvariant are calculated. If the maximum path cycle time for the path including the low Vvariant is greater than the maximum path cycle time for the path including the standard Vvariant, then that low Vvariant is substituted with a standard Vvariant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.