Stacy W Hall

US Patent:

6638145, Oct 28, 2003

Filed:

Aug 31, 2001

Appl. No.:

09/943960

Inventors:

Stacy W. Hall - San Antonio TX
Andrew J. Black - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

B24B 100

US Classification:

451 41, 451 36, 451 37, 451 57, 134 3

Abstract:

A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

US Patent:

6875089, Apr 5, 2005

Filed:

Aug 29, 2003

Appl. No.:

10/652383

Inventors:

Stacy W. Hall - San Antonio TX, US
Andrew J. Black - San Antonio TX, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

B24B001/00

US Classification:

451 41, 451 36, 451 37, 451 57, 134 3

Abstract:

A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

US Patent:

59857617, Nov 16, 1999

Filed:

Jun 19, 1996

Appl. No.:

8/666802

Inventors:

Eric A. Sparks - San Jose CA
Stacy W. Hall - San Antonio TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2144

US Classification:

438669

Abstract:

An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

US Patent:

53921135, Feb 21, 1995

Filed:

Sep 30, 1992

Appl. No.:

7/954200

Inventors:

Anthony Sayka - San Antonio TX
Stacy W. Hall - San Antonio TX
Judy U. Galloway - Fairoaks TX
Pierre Leroux - San Antonio TX
Bryan D. Schmidt - San Antonio TX
Daniel D. Siems - Boerne TX
Henry B. Taylor - San Antonio TX
Edward R. Vokoun - Boerne TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G01N 2188

US Classification:

356237

Abstract:

Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface. A selected defect, if any, on the chosen surface changes a surface characteristic of the reflecting surface so that the presence of this defect on the chosen surface is visually perceptible on the reflecting surface.

US Patent:

56400381, Jun 17, 1997

Filed:

Nov 22, 1995

Appl. No.:

8/561768

Inventors:

Eric A. Sparks - San Jose CA
Stacy W. Hall - San Antonio TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 21473

US Classification:

257412

Abstract:

An integrated circuit structure including a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

US Patent:

52698785, Dec 14, 1993

Filed:

Dec 10, 1992

Appl. No.:

7/990329

Inventors:

Allen Page - San Antonio TX
Stacy W. Hall - San Antonio TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

C23F 100
C23F 1500

US Classification:

156640

Abstract:

After a metal deposition is patterned using a plasma etch, the metal pattern is sprayed with steam and water. During the spraying the wafer is rotated to ensure proper distribution and removal of the spray. The spray removes chlorine residue from the etch that might otherwise corrode the metal pattern. After the spray, the spin rate is increased to dry the wafer. The net result is a faster and more effective method for chlorine removal from a plasma-etched metal pattern.

US Patent:

53873114, Feb 7, 1995

Filed:

Feb 16, 1993

Appl. No.:

8/017542

Inventors:

Stacy W. Hall - San Antonio TX
Miguel A. Delgado - San Antonio TX

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 21306

US Classification:

156630

Abstract:

A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.