Stanley C Keeney from Plano, TX, age 85

Us Patents

On-Chip Series Terminated Cmos(Bi-Cmos) Driver
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US Patent:

55326161, Jul 2, 1996
Filed:

Aug 1, 1994
Appl. No.:

8/283436
Inventors:

Stanley C. Keeney - Grand Saline TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03K 1716
US Classification:

326 30
Abstract:

A terminated driver circuit 10 having a controlled output impedance includes an external impedance 12 connected to a bias generator circuit 20 which is operable to generate a plurality of bias voltages in response to a reference current generated by bias generator circuit 20 wherein the reference current magnitude is a function of external impedance 12. An output driver circuit 30 is connected to bias generator circuit 20. Output driver circuit 30 has a plurality of output devices connected to a transmission line and is operable to receive the plurality of bias voltages from bias generator circuit 20 and multiplex them such that only a single bias voltage is driving a single output device at a time. The plurality of bias voltages causes the plurality of output devices to have specific, controlled impedances when conducting wherein the controlled output impedances match the characteristic impedance of a transmission line 40 being driven by terminated driver circuit 10 thereby reducing waveform reflections.

High Performance Digital Phase Locked Loop
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US Patent:

53550374, Oct 11, 1994
Filed:

Jun 15, 1992
Appl. No.:

7/898981
Inventors:

Bernhard H. Andresen - Dallas TX
Joseph A. Casasanta - Allen TX
Stanley C. Keeney - Dallas TX
Robert C. Martin - Dallas TX
Yoshinori Satoh - Plano TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03K 1728
US Classification:

307602
Abstract:

A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay path is increased, even when an edge (43) of the second waveform trails a corresponding edge (45) of the first waveform by less than one-half cycle. The delay continues to be increased until the edge of the second waveform is eventually time-shifted past the next successive corresponding edge (49) of the first waveform.

Test Input Demultiplexing Circuit
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US Patent:

46124993, Sep 16, 1986
Filed:

Nov 7, 1983
Appl. No.:

6/549121
Inventors:

Bernhard H. Andresen - Dallas TX
Stanley C. Keeney - Dallas TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

G01R 3128
US Classification:

324 73R
Abstract:

A test signal, used to initialize an integrated circuit chip for testing, is multiplexed with a data input line of the chip. The test signal circuitry is inactivated during normal operation of the chip. The test circuitry is activated only when a special input signal, which is a voltage at some midpoint between logic states, is applied to the data input.

Fine Resolution Digital Delay Line With Coarse And Fine Adjustment Stages
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US Patent:

55442030, Aug 6, 1996
Filed:

Oct 18, 1994
Appl. No.:

8/324856
Inventors:

Joseph A. Casasanta - Allen TX
Bernhard H. Andresen - Dallas TX
Yoshinori Satoh - Plano TX
Stanley C. Keeney - Dallas TX
Robert C. Martin - Dallas TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03D 324
US Classification:

375376
Abstract:

A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Integrated Circuit Having An Embedded Digital Signal Processor And Externally Testable Signal Paths
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US Patent:

58022708, Sep 1, 1998
Filed:

Mar 14, 1997
Appl. No.:

8/818618
Inventors:

Uming U-Ming Ko - Plano TX
Bernhard Hans Andresen - Dallas TX
Glen Roy Balko - Richardson TX
Stanley Clifford Keeney - Dallas TX
Joe Frank Sexton - Houston TX
Assignee:

Texas Instruments Incorporated
International Classification:

G06F 11267
US Classification:

39518303
Abstract:

An integrated circuit chip comprises a digital signal processor core (12) formed on a portion of the surface area of the chip (10). The digital signal processor (12) has a read only memory (14), a random access memory (16), a register file (18), an arithmetic logic unit (20) and a multiplier circuit (22). The remaining surface area of the integrated circuit chip (10) forms a user-definable circuitry area (24) which is used to form added circuitry to interface the digital signal processor (12) with other components of an integrated data processing system. The circuits formed in the user-definable circuitry area (24) are coupled to other integrated circuit chips through universal input/output bond pads (28). In one embodiment of the present invention, parallel module testing multiplexers (26) are added to aid in the testing of the digital signal processor (12) and the added circuits formed in the user-definable circuitry area (24).

Bicmos Buffer Circuit
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US Patent:

54303982, Jul 4, 1995
Filed:

Jan 3, 1994
Appl. No.:

8/176558
Inventors:

Michael D. Cooper - Garland TX
Robert C. Martin - Dallas TX
Stanley C. Keeney - Dallas TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03K 1920
US Classification:

326110
Abstract:

A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than present buffer circuit implementations, it provides improved transient saturation charge clamping and one buffer macro in an ASIC library can provide extended drive capability to all CMOS logic gates in the library.

Fine Resolution Digital Delay Line With Coarse And Fine Adjustment Stages
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US Patent:

58449540, Dec 1, 1998
Filed:

Feb 20, 1997
Appl. No.:

8/802498
Inventors:

Joseph A. Casasanta - Allen TX
Bernhard H. Andresen - Dallas TX
Yoshinori Satoh - Plano TX
Stanley C. Keeney - Dallas TX
Robert C. Martin - Dallas TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03D 324
US Classification:

375373
Abstract:

A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Output Buffer With Di/Dt And Dv/Dt And Tri-State Control
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US Patent:

51534576, Oct 6, 1992
Filed:

Dec 12, 1990
Appl. No.:

7/626160
Inventors:

Robert C. Martin - Dallas TX
Stanley C. Keeney - Dallas TX
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

H03K 19092
H03K 1716
US Classification:

307443
Abstract:

An output buffer (12) is provided for producing an output signal varying between a voltage on a first lien (22) and a voltage on a second line (36). First output circuitry (3, 4) is provided for pulling an output terminal (26) to the voltage on first line (22). Second output circuitry (6, 7) is provided for pulling output terminal (26) to the voltage on second line (36) in response to an input thereto. First feedback circuitry (2, 8) is provided for detecting a voltage spike on first line (22) and varying the input to first output circuitry (3 4) in response. Second feedback circuitry (5, 9) is provided for detecting a voltage spike on second line (36) and varying the input to second output circuitry (6, 7) in response.