Stephen S Chang

US Patent:

6519685, Feb 11, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/470274

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711120, 711156

Abstract:

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

US Patent:

6622214, Sep 16, 2003

Filed:

Jan 12, 1999

Appl. No.:

09/228665

Inventors:

Pete D. Vogt - Boulder CO
George P. White - Long Beach CA
Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

711141, 711124, 711146

Abstract:

A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.

US Patent:

6690221, Feb 10, 2004

Filed:

Dec 3, 1999

Appl. No.:

09/453669

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 312

US Classification:

327199, 327218, 326 94

Abstract:

An apparatus includes a first latch having an output terminal. A latch signal is received by the first latch. A second receives the latch signal and having an input terminal coupled to the output terminal of the first latch. A delay circuit delays the latch signal to the first latch.

US Patent:

6694409, Feb 17, 2004

Filed:

Feb 10, 2003

Appl. No.:

10/361542

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711156

Abstract:

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

US Patent:

6930522, Aug 16, 2005

Filed:

Jan 6, 2004

Appl. No.:

10/752770

Inventors:

Stephen S. Chang - Glendora CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L007/00

US Classification:

327154, 327199, 326 94

Abstract:

A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.

US Patent:

7028299, Apr 11, 2006

Filed:

Jun 30, 2000

Appl. No.:

09/608869

Inventors:

Stephen S. Chang - Glendora CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718104, 718102, 718107, 707 8, 707 9

Abstract:

An embodiment of the present invention is a task manager to manage tasks in a multiprocessor system. A task table stores task entries corresponding to tasks executed by at least one processor. A block allocation circuit allocates blocks of the cache memory used by the tasks. A task coordinator coordinates the tasks in response to a task cycle issued by a processor.

US Patent:

7530066, May 5, 2009

Filed:

Jun 24, 2002

Appl. No.:

10/179790

Inventors:

Stephen S. Chang - Glendora CA, US

International Classification:

G06F 9/46
G06F 13/00
G06F 13/24

US Classification:

718100, 710100, 710260, 711141, 711146

Abstract:

An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition.

US Patent:

7558923, Jul 7, 2009

Filed:

Dec 22, 1999

Appl. No.:

09/470329

Inventors:

Brian R. Bennett - Laguna Niguel CA, US
Stephen S. Chang - Glendora CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08
G06F 13/18
G06F 5/00

US Classification:

711144, 711151, 711152, 711158, 711166, 710200, 710244, 710 52

Abstract:

Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.