Stephen Yaw Chang

US Patent:

8111615, Feb 7, 2012

Filed:

Jul 7, 2008

Appl. No.:

12/168616

Inventors:

Stephen S. Chang - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04J 3/14

US Classification:

370221, 37039531, 711121

Abstract:

A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node.

US Patent:

20110286458, Nov 24, 2011

Filed:

May 24, 2011

Appl. No.:

13/114644

Inventors:

Stephen S. Chang - Portland OR, US

International Classification:

H04L 12/56

US Classification:

370392

Abstract:

A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node.

US Patent:

20130279622, Oct 24, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/976680

Inventors:

Venkatraman Iyer - Austin TX, US
Santanu Chaudhuri - Mountain View CA, US
Stephen S. Chang - Portland OR, US

International Classification:

H04L 1/00

US Classification:

375285

Abstract:

A method and system to reduce the power supply noise of a platform during the training of high speed communication links. In one embodiment of the invention, the device has logic to stagger a bit lock pattern for each of one or more communication links and scramble a training sequence for each of the one or more communication links. By doing so, it removes the need for anti-noise circuits and in turn, reduces the silicon area and power of the devices. Further, by having the logic in the physical layers to facilitate the training of the communication links, it eliminates the need to redesign the package of the devices to shift the resonant frequencies.

US Patent:

20200026556, Jan 23, 2020

Filed:

Sep 26, 2019

Appl. No.:

16/584716

Inventors:

- Santa Clara CA, US
Mariano Aguirre - Portland OR, US
Stephen S. Chang - Hillsboro OR, US
Rohan Menezes - Hillsboro OR, US
Michael T. Werstlein - Portland OR, US
Jonathan Lo - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/48
G06F 9/455
G06F 12/0882
G06F 12/1081
G06F 13/16

Abstract:

A server having a host processor coupled to a programmable coprocessor is provided. One or more virtual machines may run on the host processor. The coprocessor may be coupled to an auxiliary memory that stores virtual machine (VM) states. During live migration, the coprocessor may determine when to move the VM states from the auxiliary memory to a remote server node. The coprocessor may include a coherent protocol home agent and state tracking circuitry configured to track data modification at a cache line granularity. Whenever a particular cache line has been modified, only the data associated with that cache line will be moved to the remote server without having to copy over the entire page, thereby substantially reducing the amount of data that needs to be transferred during migration events.

US Patent:

20190042518, Feb 7, 2019

Filed:

Dec 9, 2017

Appl. No.:

15/836856

Inventors:

- Santa Clara CA, US
Stephen S. Chang - Hillsboro OR, US
Nagabhushan Chitlur - Portland OR, US
Michael C. Adler - Newton MA, US

International Classification:

G06F 13/42
G06N 3/08
G06F 9/455

Abstract:

There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.

US Patent:

20140281276, Sep 18, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/827695

Inventors:

Pratik M. Marolia - Hillsboro OR, US
Nagabhushan Chitlur - Portland OR, US
Stephen S. Chang - Portland OR, US

International Classification:

G06F 12/08

US Classification:

711146

Abstract:

A method, apparatus, computer program product, and computer readable medium to perform receipt of a snoop notification indicating a write to a memory address associated with a cache, determination that the snoop notification signifies receipt of a message based, at least in part, on the memory address, and performance of an operation based, at least in part, on the message is disclosed.