Stephen D Chang

US Patent:

6519685, Feb 11, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/470274

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711120, 711156

Abstract:

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

US Patent:

6690221, Feb 10, 2004

Filed:

Dec 3, 1999

Appl. No.:

09/453669

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 312

US Classification:

327199, 327218, 326 94

Abstract:

An apparatus includes a first latch having an output terminal. A latch signal is received by the first latch. A second receives the latch signal and having an input terminal coupled to the output terminal of the first latch. A delay circuit delays the latch signal to the first latch.

US Patent:

6694409, Feb 17, 2004

Filed:

Feb 10, 2003

Appl. No.:

10/361542

Inventors:

Stephen S. Chang - Glendora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711156

Abstract:

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

US Patent:

6930522, Aug 16, 2005

Filed:

Jan 6, 2004

Appl. No.:

10/752770

Inventors:

Stephen S. Chang - Glendora CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L007/00

US Classification:

327154, 327199, 326 94

Abstract:

A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.

US Patent:

7028299, Apr 11, 2006

Filed:

Jun 30, 2000

Appl. No.:

09/608869

Inventors:

Stephen S. Chang - Glendora CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718104, 718102, 718107, 707 8, 707 9

Abstract:

An embodiment of the present invention is a task manager to manage tasks in a multiprocessor system. A task table stores task entries corresponding to tasks executed by at least one processor. A block allocation circuit allocates blocks of the cache memory used by the tasks. A task coordinator coordinates the tasks in response to a task cycle issued by a processor.

US Patent:

7530066, May 5, 2009

Filed:

Jun 24, 2002

Appl. No.:

10/179790

Inventors:

Stephen S. Chang - Glendora CA, US

International Classification:

G06F 9/46
G06F 13/00
G06F 13/24

US Classification:

718100, 710100, 710260, 711141, 711146

Abstract:

An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition.

US Patent:

20130345094, Dec 26, 2013

Filed:

Nov 30, 2012

Appl. No.:

13/691258

Inventors:

New York Stem Cell Foundation - , US
Kevin C. Eggan - Boston MA, US
Stephen Chang - Poway CA, US
Susan Solomon - New York NY, US

Assignee:

New York Stem Cell Foundation - New York NY

International Classification:

C12N 5/074

US Classification:

506 14, 4352851, 4353051, 435377, 4352871

Abstract:

The invention provides an automated system for producing induced pluripotent stem cells (iPSCs) from adult somatic cells. Further, the system is used for producing differentiated adult cells from stem cells. The invention system is useful for isolating somatic cells from tissue samples, producing iPSC lines from adult differentiated cells by reprogramming such cells, identifying the pluripotent reprogrammed adult cells among other cells, and expanding and screening the identified reprogrammed cells.

US Patent:

39502660, Apr 13, 1976

Filed:

Nov 28, 1973

Appl. No.:

5/419715

Inventors:

Stephen S. Chang - East Brunswick NJ
Cheng-Li Huang - Piscataway NJ
An-Li Hsieh - New Brunswick NJ

Assignee:

Rutgers Research and Educational Foundation - New Brunswick NJ

International Classification:

C09K 1534
A23B 400
A23L 128

US Classification:

252398

Abstract:

Antioxidant compositions, useful for preventing deterioration of oils and fats in food products, are prepared by a two-stage extraction from rosemary or sage. A crude product is first extracted from the plant material with a low-boiling solvent separable by evaporation, and is then found to be separable from contaminants that cause objectionable taste or odor, by vacuum steam or molecular distillation, with the antioxidant in a suitable oil carrier, and with the contaminants removed in vapor state. A special purification of the extract, for a product of very high purity except for some flavor or odor for which distillation may be needed, is attainable by chromatography, wherein the antioxidant material favors solvents of greater polarity than solvents in which other materials are eluted. The new antioxidant compositions are not only widely useful but appear to have unusual value in respect to vegetable oils and in respect to oils used in deep frying, and also are found of special value for inhibiting certain flavor and odor effects that occur in soybean oil.