Stephen E Greco

US Patent:

6339022, Jan 15, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/475712

Inventors:

Arne W. Ballantine - Coldspring NY
Cheryl G. Faltermeier - Lagrange NY
Jeffrey D. Gilbert - Burlington VT
Ronald D. Goldblatt - Yorktown Heights NY
Nancy A. Greco - Lagrangeville NY
Stephen E. Greco - Lagrangeville NY
Frank V. Liucci - Wappingers Falls NY
Glenn Robert Miller - Essex Junction VT
Bruce A. Root - Westford VT
Andrew H. Simon - Fishkill NY
Anthony K. Stamper - Williston VT
Ronald A. Warren - Essex Junction VT
David H. Yao - Essex VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438660, 438663, 438687

Abstract:

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

US Patent:

6348736, Feb 19, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/429257

Inventors:

Vincent J. McGahay - Poughkeepsie NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY
Robert Cook - Minneapolis MN
Stephen E. Greco - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257774, 257762, 257773

Abstract:

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

US Patent:

6451712, Sep 17, 2002

Filed:

Dec 18, 2000

Appl. No.:

09/739935

Inventors:

Timothy Joseph Dalton - Ridgefield CT
Stephen Edward Greco - Lagrangeville NY
Jeffrey Curtis Hedrick - Montvale NJ
Satyanarayana V. Nitta - Fishkill NY
Sampath Purushothaman - Yorktown Heights NY
Kenneth Parker Rodbell - Sandy Hook CT
Robert Rosenberg - Cortlandt Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2131

US Classification:

438781, 438780, 438622

Abstract:

A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i. e. smaller than 2. 6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

US Patent:

6479884, Nov 12, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/893786

Inventors:

Robert Cook - Minneapolis MN
Stephen E. Greco - LaGrangeville NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Vincent J. McGahay - Poughkeepsie NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2358

US Classification:

257642, 257643, 257773, 257774, 438623

Abstract:

Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

US Patent:

6573606, Jun 3, 2003

Filed:

Jun 14, 2001

Appl. No.:

09/881444

Inventors:

Carlos Juan Sambucetti - Croton on Hudson NY
Xiaomeng Chen - Poughkeepsie NY
Birenda Nath Agarwala - Hopewell Juction NY
Chao-Kun Hu - Somers NY
Naftali Eliahu Lustig - Croton on Hudson NY
Stephen Edward Greco - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

257762, 257750, 257751, 257763, 257764, 257765, 257770, 257771, 438612, 438618, 438633, 438687

Abstract:

In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type AâXâY, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

US Patent:

6727589, Apr 27, 2004

Filed:

Nov 30, 2000

Appl. No.:

09/725862

Inventors:

Stephen E. Greco - LaGrangeville NY
John P. Hummel - Millbrook NY
Joyce Liu - Hopewell Junction NY
Vincent J. McGahay - Poughkeepsie NY
Rebecca Mih - Wappingers Falls NY
Kamalesh Srivastava - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257751, 257750, 257752, 257758, 257642, 257643, 257774, 257761, 257762, 257763, 257764, 257765, 257766

Abstract:

A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

US Patent:

6734096, May 11, 2004

Filed:

Jan 17, 2002

Appl. No.:

10/053288

Inventors:

Timothy J. Dalton - Ridgefield CT
Michael D. Armacost - San Jose CA
Stephen M. Gates - Ossining NY
Stephen E. Greco - LaGrangeville NY
Simon M. Karecki - late of Brooklyn NY
Satyanarayana V. Nitta - Poughquag NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 214763

US Classification:

438624, 438634, 438637, 438692, 438717, 438736

Abstract:

A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 , preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.

US Patent:

6784105, Aug 31, 2004

Filed:

Apr 9, 2003

Appl. No.:

10/410496

Inventors:

Chih-Chao Yang - Beacon NY
Yun Wang - Hopewell Junction NY
Larry Clevenger - Hopewell Junction NY
Andrew Simon - Fishkill NY
Stephen Greco - Hopewell Junction NY
Kaushik Chanda - Poughkeepsie NY
Terry Spooner - Hopewell Junction NY
Andy Cowley - Wappingers Falls NY

Assignee:

Infineon Technologies North America Corp. - San Jose CA
International Business Machines Corporation - Armonk NY
United Microelectronics Co.

International Classification:

H01L 2144

US Classification:

438687, 438637, 438643, 438653, 438675, 438685, 438688

Abstract:

A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.