Stephen J Greco

US Patent:

7941780, May 10, 2011

Filed:

Apr 18, 2008

Appl. No.:

12/105299

Inventors:

Albrik Avanessian - Watertown MA, US
Dureseti Chidambarrao - Weston CT, US
Stephen E. Greco - Lagrangeville NY, US
Douglas W. Kemerer - Essex Junction VT, US
Tina Wagner - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716132, 716 51, 716 52, 716100, 716110, 716135

Abstract:

A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i. e. , the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.