Stephen C Greco

US Patent:

6573606, Jun 3, 2003

Filed:

Jun 14, 2001

Appl. No.:

09/881444

Inventors:

Carlos Juan Sambucetti - Croton on Hudson NY
Xiaomeng Chen - Poughkeepsie NY
Birenda Nath Agarwala - Hopewell Juction NY
Chao-Kun Hu - Somers NY
Naftali Eliahu Lustig - Croton on Hudson NY
Stephen Edward Greco - Lagrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

257762, 257750, 257751, 257763, 257764, 257765, 257770, 257771, 438612, 438618, 438633, 438687

Abstract:

In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type AâXâY, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

US Patent:

8117568, Feb 14, 2012

Filed:

Sep 25, 2008

Appl. No.:

12/237727

Inventors:

Hua Xiang - Ossining NY, US
Laertis Economikos - Wappingers Falls NY, US
Mohammed F. Fayaz - Pleasantville NY, US
Stephen E. Greco - Lagrangeville NY, US
Patricia A. O'Neil - Newburgh NY, US
Ruchir Puri - Baldwin Place NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716100, 716126, 716132, 703 14

Abstract:

Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

US Patent:

20150255342, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721323

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255343, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721361

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255398, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721410

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 23/532

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20140203435, Jul 24, 2014

Filed:

Jan 18, 2013

Appl. No.:

13/744705

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton on Hudson NY, US
Andrew H. Simon - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768
H01L 23/532

US Classification:

257751, 438643

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.