Stephen J Gualandri

US Patent:

6477082, Nov 5, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751688

Inventors:

Theodore T. Pekny - Campbell CA
Stephen J. Gualandri - Campbell CA

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1134

US Classification:

36518511, 36523006

Abstract:

A memory device has a segmented memory cell array that take a row address and a column address and allows for data words in a column page to be read internally in parallel for faster access. The memory device employs a segmented memory array that routes column address and column address+1 to the segments. This allows for a random starting data word in the column page, while the data words in the next column page (column address+1) are loaded into the memory array segments before the starting data word. When the data page mode or linear burst access crosses a column address boundary the next data words in column address+1 are available and no wait states need to be asserted to allow for new column address values to propagate.

US Patent:

6714458, Mar 30, 2004

Filed:

Feb 11, 2002

Appl. No.:

10/074453

Inventors:

Stephen J. Gualandri - Campbell CA
Theodore T. Pekny - Milpitas CA

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1614

US Classification:

36518529, 36518533, 36518525, 365204

Abstract:

An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.

US Patent:

6791893, Sep 14, 2004

Filed:

Jun 12, 2002

Appl. No.:

10/170161

Inventors:

Theodore T. Pekny - Miltitas CA
Stephen J. Gualandri - Campbell CA

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365226, 36518518, 36518909

Abstract:

The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.

US Patent:

6868016, Mar 15, 2005

Filed:

Jan 29, 2004

Appl. No.:

10/768573

Inventors:

Stephen J. Gualandri - Campbell CA, US
Theodore T. Pekny - Milpitas CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C016/14
G11C016/16

US Classification:

36518529, 36518533, 36518525, 365204

Abstract:

An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.

US Patent:

6937517, Aug 30, 2005

Filed:

Jul 18, 2002

Appl. No.:

10/197782

Inventors:

Theodore T. Pekny - Milititas CA, US
Stephen J. Gualandri - Campbell CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C016/04
G11C016/06

US Classification:

36518518, 36518522, 36518529, 36518533

Abstract:

The present invention provides a method and apparatus for regulating clocks for varying loads. The method includes providing a regulated signal of a first amplitude during a first operating mode and a regulated signal of a second amplitude during a second operation mode. The method further includes driving at least one of a first load and a second load based on the regulated signal.

US Patent:

7173869, Feb 6, 2007

Filed:

Aug 13, 2004

Appl. No.:

10/917608

Inventors:

Theodore T. Pekny - Miltitas CA, US
Stephen J. Gualandri - Campbell CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365222, 36518909, 365228

Abstract:

The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.

US Patent:

7200047, Apr 3, 2007

Filed:

Mar 14, 2005

Appl. No.:

11/080351

Inventors:

Stephen J. Gualandri - Campbell CA, US
Theodore T. Pekny - Milpitas CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 16/14
G11C 16/16

US Classification:

36518529, 36518533, 36518525, 365204

Abstract:

An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.

US Patent:

7248521, Jul 24, 2007

Filed:

Jul 12, 2005

Appl. No.:

11/178683

Inventors:

Vipul Patel - San Jose CA, US
Stephen Gualandri - Morgan Hill CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 11/34

US Classification:

365204, 36518525

Abstract:

Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e. g. , erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.