Stephen K Hamilton

US Patent:

8407433, Mar 26, 2013

Filed:

Jun 24, 2008

Appl. No.:

12/144883

Inventors:

Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US

Assignee:

Sonics, Inc. - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711157, 711201

Abstract:

In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

US Patent:

20080320254, Dec 25, 2008

Filed:

Jun 24, 2008

Appl. No.:

12/145052

Inventors:

Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US

Assignee:

Sonics, Inc. - Milpitas CA

International Classification:

G06F 12/06

US Classification:

711157, 711105, 711E12083, 711E12079

Abstract:

A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

US Patent:

20080320255, Dec 25, 2008

Filed:

Jun 24, 2008

Appl. No.:

12/145257

Inventors:

Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US

Assignee:

Sonics, Inc. - Milpitas CA

International Classification:

G06F 12/02

US Classification:

711157, 711E12005

Abstract:

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

US Patent:

20080320476, Dec 25, 2008

Filed:

Jun 24, 2008

Appl. No.:

12/144987

Inventors:

Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US

Assignee:

Sonics, Inc. - Milpitas CA

International Classification:

G06F 9/46

US Classification:

718101

Abstract:

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

US Patent:

20120036296, Feb 9, 2012

Filed:

Oct 18, 2011

Appl. No.:

13/276041

Inventors:

Drew E. Wingard - Palo Alto CA, US
Chien-Chun Chou - Saratoga CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Ian Andrew Swarbrick - Sunnyvale CA, US
Vida Vakilotojar - Mountain View CA, US

Assignee:

SONICS, INC. - Milpitas CA

International Classification:

G06F 13/42

US Classification:

710105

Abstract:

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.

US Patent:

20130329842, Dec 12, 2013

Filed:

Jun 7, 2012

Appl. No.:

13/490729

Inventors:

William John Bainbridge - Menlo Park CA, US
Stephen W. Hamilton - Pembroke Pines FL, US
Neal T. Wingen - Inverness IL, US

Assignee:

SONICS, INC. - Milpitas CA

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

US Patent:

20150051381, Feb 19, 2015

Filed:

Aug 7, 2014

Appl. No.:

14/454044

Inventors:

- Lebanon NH, US
Stefan Wildt - Somerville MA, US
Byung-kwon Choi - Hanover NH, US
Juergen Hermann Nett - Grantham NH, US
Piotr Bobrowicz - Hanover NH, US
Stephen R. Hamilton - Lebanon NH, US
Robert C. Davidson - Hanover NH, US

International Classification:

C12P 21/00
C07K 14/47

US Classification:

530395, 435 681, 506 16, 435366

Abstract:

The present invention relates to eukaryotic host cells having modified oligosaccharides which may be modified further by heterologous expression of a set of glycosyltransferases, sugar transporters and mannosidases to become host-strains for the production of mammalian, e.g., human therapeutic glycoproteins. The invention provides nucleic acid molecules and combinatorial libraries which can be used to successfully target and express mammalian enzymatic activities such as those involved in glycosylation to intracellular compartments in a eukaryotic host cell. The process provides an engineered host cell which can be used to express and target any desirable gene(s) involved in glycosylation. Host cells with modified oligosaccharides are created or selected. N-glycans made in the engineered host cells have a ManGlcNAccore structure which may then be modified further by heterologous expression of one or more enzymes, e.g., glycosyltransferases, sugar transporters and mannosidases, to yield human-like glycoproteins. For the production of therapeutic proteins, this method may be adapted to engineer cell lines in which any desired glycosylation structure may be obtained.