Stephen D Hill

US Patent:

6513053, Jan 28, 2003

Filed:

Jan 12, 2000

Appl. No.:

09/481438

Inventors:

Stephen John Hill - Austin TX

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 700

US Classification:

708210, 708211, 712225

Abstract:

An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to be found more quickly. This has particular application to block memory loads and block stores to memory, wherein ones in the register list in the instruction word indicate the registers to be loaded or stored. Thus, in these applications the present invention enables the positions of these ones to be determined quickly.

US Patent:

6550005, Apr 15, 2003

Filed:

Nov 29, 1999

Appl. No.:

09/449867

Inventors:

Stephen John Hill - Austin TX

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 930

US Classification:

712245, 712226, 712219, 712227, 714 17

Abstract:

Apparatus ( ) and method for processing data in response to a sequence of program instructions including a primary pipelined processing unit ( ) for performing data processing, the primary pipelined processing unit being responsive to a cancellation condition such as an abort to cancel processing of a partially completed program instruction. The apparatus and method comprising a pseudo instruction generator ( ) to generate a pseudo instruction to a fix-up pipelined processing unit ( ) in response to a program instruction (LDM, STM) that can be subject to cancellation, the pseudo instruction controlling the fix-up pipelined processing unit to produce a state in which the partially completed program instruction may be re-executed at a later time.

US Patent:

6990569, Jan 24, 2006

Filed:

Oct 25, 2001

Appl. No.:

09/983779

Inventors:

Stephen John Hill - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 9/00

US Classification:

712227, 712208

Abstract:

A data processing apparatus is provided comprising: a processor operable to execute instructions, each instruction having a micro-architectural state information associated therewith; comparator logic operable to compare the micro-architectural state information with predetermined micro-architectural state information associated with a problematic event and to issue a match signal if a match is detected; and trigger logic responsive to the match signal to provide one of a plurality of output signals, the trigger logic being programmable to determine which of the output signals is provided upon receipt of the match signal, each output signal being arranged to activate a corresponding mechanism to handle the problematic event. This advantageous arrangement alleviates problems encountered by prior art approaches by providing a programmable mechanism to identify a problematic event and to activate an appropriate mechanism to handle that problematic event. Hence, even after the hardware design of the processor has been finalised, problematic events can be identified and a mechanism activated to handle those problematic events once detected by the data processing apparatus, without requiring the faulty hardware to be modified, or the body of the software to be rewritten.

US Patent:

7174472, Feb 6, 2007

Filed:

May 20, 2003

Appl. No.:

10/441267

Inventors:

Stephen John Hill - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 13/14

US Classification:

713323, 713300, 713310, 713320, 713321, 713324, 713330, 713340

Abstract:

An integrated circuit provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down mode. Prior to removing the main power supply execution of data processing instructions within the instruction pipeline preceding a restart instruction are completed so as to reduce the amount of state data which needs to be stored across the power down event. Thus, a compromise is achieved between rapid power down through the use of dedicated storage cells and the circuit area requirements of such storage cells and the need to complete execution of some partially executed data processor instructions within the instruction pipeline and other operations such as, pending writes within the integrated circuit. The trigger event to trigger power down or power up may be a signal on an external pin, an internally generated signal within the integrated circuit execution of a specific data processing instruction, or other events.

US Patent:

7234043, Jun 19, 2007

Filed:

Mar 7, 2005

Appl. No.:

11/072644

Inventors:

Conrado Blasco Allue - Austin TX, US
Glen Andrew Harris - Austin TX, US
Stephen John Hill - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/44

US Classification:

712226

Abstract:

Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

US Patent:

7293212, Nov 6, 2007

Filed:

Mar 22, 2005

Appl. No.:

11/085599

Inventors:

Conrado Blasco Allue - Austin TX, US
Stephen John Hill - Austin TX, US
Richard Slobodnik - Austin TX, US

Assignee:

ARM Limted - Cambridge

International Classification:

G01R 31/28
G11C 29/00
G11C 7/00

US Classification:

714733, 714718, 365201

Abstract:

A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

US Patent:

7389459, Jun 17, 2008

Filed:

Mar 22, 2005

Appl. No.:

11/085598

Inventors:

Conrado Blasco Allue - Austin TX, US
Stephen John Hill - Austin TX, US
David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G01R 31/28
G11C 29/00
G11C 7/00

US Classification:

714733, 714718, 365201

Abstract:

A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.

US Patent:

7496899, Feb 24, 2009

Filed:

Aug 17, 2005

Appl. No.:

11/205310

Inventors:

Stephen John Hill - Austin TX, US
Glen Andrew Harris - Austin TX, US
David James Williamson - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/44
G06F 9/00

US Classification:

717127, 717128, 712227, 712216, 712214

Abstract:

Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when to issue a decoded instructions for execution by execution logic; execution logic operable to execute the decoded instructions; interface logic selectively operable to receive trace information relating to the state of the data processing apparatus generated in response to execution of the decoded instructions for transmission to trace monitoring infrastructure; and throttle logic operable to predict whether issuing the decoded instruction to the execution logic for execution would be likely to cause the trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent the decode/issue logic from issuing the decoded instruction to the execution logic. Accordingly, the throttle logic reviews each instruction to be executed and predicts whether issuing that instruction at that time will or is likely to cause the capacity to be exceeded. In the event that the throttle logic determines that the capacity is likely to be exceeded, the instruction is prevented from being issued to the execution logic which reduces the likelihood that any state information is lost.