Stephen A Jenkins

US Patent:

40471578, Sep 6, 1977

Filed:

Feb 1, 1974

Appl. No.:

5/438952

Inventors:

Stephen R. Jenkins - Acton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 300

US Classification:

364900

Abstract:

A controller for use in a data processing system for coupling a direct access storage element to the system. The controller contains a control path for routing control information from the system to various circuits in the controller and designated storage elements to enable a transfer of data stored on the medium over a data path in the controller. The controller data path also couples the medium to the system and includes a switching network which permits the data to be selectively coupled to or from one of two separate system buses. Control information routed to the controller identifies the system to be involved in a transfer and routing circuits in the controller provide the connection between the controller and designated systems.

US Patent:

40558517, Oct 25, 1977

Filed:

Feb 13, 1976

Appl. No.:

5/658113

Inventors:

Stephen R. Jenkins - Acton MA
Thomas A. Northrup - Westford MA
Robert E. Stewart - Stow MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1306

US Classification:

364200

Abstract:

A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. It is possible for the associative memory unit to request successive transfers with one or more memory modules on an overlapped basis.

US Patent:

41515935, Apr 24, 1979

Filed:

Jun 9, 1977

Appl. No.:

5/804942

Inventors:

Stephen R. Jenkins - Acton MA
Thomas A. Northrup - Westford MA
Robert E. Stewart - Stow MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module. In addition, each memory module contains a margin bit decoder that decodes various binary margin signals that are transferred to it for performing various control operations.

US Patent:

47697687, Sep 6, 1988

Filed:

Oct 9, 1986

Appl. No.:

6/917319

Inventors:

Frank C. Bomba - Andover MA
Stephen R. Jenkins - Acton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1314
G06F 1336
G06F 1340

US Classification:

364200

Abstract:

A process for directing an interrupt request from an interrupting device to a selected number of processing devices by a bus. The interrupting device asserts one or more data lines during an interrupt command, each asserted data line corresponding to a selected processing device to which the interrupt command is directed. During an identify transaction, the interrupting device monitors which data line is asserted by a processing device to determine whether the asserted data line corresponds to a processing device selected by a destination mask stored in the interrupting device. Subsequently, one or more data lines are asserted by the interrupting device corresponding to a particular interrupt routine. The interrupting device itself selects particular processing devices, eliminating the need for a central interrupt arbiter. The process allows the interrupting device to seek interrupt servicing from any number of other devices, and to accept service from the first device which is available.

US Patent:

41492390, Apr 10, 1979

Filed:

Oct 25, 1977

Appl. No.:

5/845220

Inventors:

Stephen R. Jenkins - Acton MA
Thomas A. Northrup - Westford MA
Robert E. Stewart - Stow MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 306
G06F 1300
G06F 1306

US Classification:

364200

Abstract:

A secondary storage facility that connects to a digital data processing system. The system includes a central processor, an associative memory and a random access memory connected to the associative memory. The secondary storage facility includes a controller and one or more direct access secondary storage units. A first bus connector interconnects the controller to a first bus from the central processor and transfers of control information are routed over this bus. The controller also connects to the associative memory so that data, together with address and control information, is routed between the random access memory and a storage unit through this second connection.

US Patent:

47632496, Aug 9, 1988

Filed:

Oct 29, 1986

Appl. No.:

6/924578

Inventors:

Frank C. Bomba - Andover MA
Reinhard Schumann - Stow MA
Stephen R. Jenkins - Acton MA
Paul Binder - Coral Springs FL

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1314
G06F 1338
G06F 1340

US Classification:

364200

Abstract:

A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

US Patent:

47061901, Nov 10, 1987

Filed:

Jul 16, 1985

Appl. No.:

6/755952

Inventors:

Frank C. Bomba - Andover MA
Stephen R. Jenkins - Acton MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1342

US Classification:

364200

Abstract:

When a device on a computer communications bus receives a request to enter into a transaction and is not yet ready to perform the transaction, it sends a retry signal to the requesting device to indicate to it that it should terminate the transaction that it has initiated. If the responding device may later be ready to engage in the transaction if the transaction is initiated again some time in the future, the signal is a retry signal and differs from the signal that the requesting device would receive if the transaction were to be terminated for some other reason. As a result, the master device can be arranged to re-initiate only those transactions for which there is a likelihood that they can be carried out to completion when they are attempted again.