Stephen A Lee

US Patent:

6762973, Jul 13, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/322215

Inventors:

Chenming W. Tung - Fremont CA
Stephen Lee - Santa Clara CA

Assignee:

Giga Semiconductor, Inc. - Santa Clara CA

International Classification:

G11C 1300

US Classification:

365233, 365239

Abstract:

The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.

US Patent:

6806692, Oct 19, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/303107

Inventors:

Stephen Lee - Santa Clara CA

Assignee:

Giga Semiconductor, Inc. - Santa Clara CA

International Classification:

G05F 1573

US Classification:

323277, 323282

Abstract:

A voltage down converter for providing a supply voltage and current to a device, such as a semiconductor device. The voltage down converter includes a first circuit that supplies steady state or âDCâ current to the device, and a second circuit that supplies the fluctuating or âACâ current to the device. The first circuit includes a first comparator that drives a first transistor P to supply most of the steady state current. The second circuit includes a second comparator , which is larger than the first comparator , and which drives a second transistor P , which is smaller than the first transistor P , to supply the fluctuating current to the device. The converter further includes a feedback circuit for controlling the supply voltage.

US Patent:

7292490, Nov 6, 2007

Filed:

Sep 8, 2005

Appl. No.:

11/223194

Inventors:

Stephen Lee - Campbell CA, US

Assignee:

GSI Technology, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365222, 365233

Abstract:

The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.

US Patent:

7509504, Mar 24, 2009

Filed:

Sep 30, 2004

Appl. No.:

10/956219

Inventors:

Kleanthes G. Koniaris - Palo Alto CA, US
Stephen Lee - Los Altos CA, US
Mark Hennecke - Cupertino CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 327537

Abstract:

Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

US Patent:

D613294, Apr 6, 2010

Filed:

Sep 8, 2006

Appl. No.:

29/248906

Inventors:

Stephen Lee - San Francisco CA, US
Lawrence Lam - San Jose CA, US
Troy Hulik - Saratoga CA, US

Assignee:

Palm, Inc. - Sunnyvale CA

International Classification:

1402

US Classification:

D14439, D14346

US Patent:

7721322, May 18, 2010

Filed:

Mar 22, 2006

Appl. No.:

11/387644

Inventors:

Ramana Rao Turlapati - Fremont CA, US
Saurabh Shrivastava - Fremont CA, US
Stephen Man Lee - San Francisco CA, US
Raymond K. Ng - San Jose CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

H04L 29/00

US Classification:

726 1, 726 3, 726 8, 709206, 713201

Abstract:

Embodiments of the invention provide a trust framework for governing service-to-service interactions. This trust framework can provide enhanced security and/or manageability over prior systems. Merely by way of example, in some cases, an information store can be used to store information security information (such as trust information, credentials, etc. ) for a variety of services across an enterprise. In other cases, the trust framework can provide authentication policies to define and/or control authentication between services (such as, for example, types of authentication credentials and/or protocols are required to access a particular service—either as a user and/or as another service—and/or types of authentication credentials and/or protocols a service may be enabled to use to access another service). Alternatively and/or additionally, the trust framework can provide authorization policies to define and/or control authorization between services.

US Patent:

8116161, Feb 14, 2012

Filed:

Oct 15, 2007

Appl. No.:

11/872675

Inventors:

Stephen Lee - Campbell CA, US

Assignee:

GSI Technology, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365222, 36523002, 36523006, 3652331

Abstract:

The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.

US Patent:

8127156, Feb 28, 2012

Filed:

Mar 24, 2009

Appl. No.:

12/410249

Inventors:

Kleanthes G. Koniaris - Palo Alto CA, US
Stephen Lee - Los Altos CA, US
Mark Hennecke - Cupertino CA, US

International Classification:

G06F 1/26

US Classification:

713300, 327537

Abstract:

Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

Address:

12127 Boheme Dr, Houston, TX 77024

VIN:

1GNFC13037R162835

Make:

CHEVROLET

Model:

TAHOE C1500

Year:

2007