Stephen N Levine

US Patent:

6498809, Dec 24, 2002

Filed:

Jan 20, 1998

Appl. No.:

09/009149

Inventors:

Frederick D. Dean - Chicago IL
James C. Brailean - Park Ridge IL
Stephen N. Levine - Itasca IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04N 712

US Classification:

375240, 3488451

Abstract:

A video bitstrean error resilient transcoder ( ), method ( ), video-phone, and video-communicator are provided wherein error resilience is implemented by verifying a syntax of a video bitstream and replacing the video bitstream between resynchronization markers with a valid syntax that is used by a decoder to produce a video sequence.

US Patent:

46175202, Oct 14, 1986

Filed:

Jan 3, 1984

Appl. No.:

6/567714

Inventors:

Stephen N. Levine - Chicago IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 1300
H03K 906
H03L 700

US Classification:

328133

Abstract:

A digital lock detector for a phase-locked loop accumulates out-of-lock pulses which are derived from a high frequency clock signal. The out-of-lock pulses are gated by an out-of-phase indicator signal and a pulse centered around the phase-locked loop output cycles to reduce the effect of relative phase jitter between the input and output signals of the phase-locked loop. The digital lock detector utilizes two counters in series which are reset independently to provide resistance to fading signal conditions. In addition, the lock detector circuit requires several consecutive long out-of-lock indications before an out-of-lock condition is indicated.

US Patent:

45730172, Feb 25, 1986

Filed:

Jan 3, 1984

Appl. No.:

6/567724

Inventors:

Stephen N. Levine - Chicago IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 513
H03K 522
H03D 1300

US Classification:

328155

Abstract:

A unitary phase and frequency adjust network for use in a multiple frequency digital phase-locked loop circuit is described. The unitary phase and frequency adjust network utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The phase and frequency adjust network effects frequency shifts by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controlled clock signal.

US Patent:

46689176, May 26, 1987

Filed:

Mar 26, 1986

Appl. No.:

6/843875

Inventors:

Stephen N. Levine - Chicago IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 906
H03K 513

US Classification:

328133

Abstract:

A phase comparator circuit for use with a digital phase-locked loop which can be programmably altered to provide phase comparisons either on the leading edge or leading and trailing edges of the phase-locked loop output signal, to provide an increased operating bandwidth capability to the phase comparator circuit. The phase comparator circuit can be configured to cooperate with a multiple frequency digital phase-locked loop such that the results of a phase comparison will be delayed until a frequency adjustment has been completed.

US Patent:

48767409, Oct 24, 1989

Filed:

Feb 13, 1989

Appl. No.:

7/310013

Inventors:

Stephen N. Levine - Chicago IL
Albert J. Leitich - Chicago IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04Q 704

US Classification:

455 33

Abstract:

A cellular radiotelephone system is disclosed in which the signalling protocol for the system is embedded in the frame synchronization of the digital messages transmitted on the system. Multiple functions are accomplished by the synchronization signal and include call supervision, mode definition, and data frame synchronization. The synchronization signal is a high auto correlation, low cross correlation sequence of a predetermined number of data bits. Different bit sequences may be employed as a synchronization signal while conveying call supervision information defining the serving fixed site. Additionally, the logical inverse of the synchronizing signal may be utilized interchangably with the synchronizing signal to define the fixed site. A repetitive pattern of synchronizing signals and logical inverse synchronizing signals convey system mode information without increasing signalling overhead or losing the correlation performance of the full synchronization word.

US Patent:

46495436, Mar 10, 1987

Filed:

Aug 30, 1985

Appl. No.:

6/771458

Inventors:

Stephen N. Levine - Chicago IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1100

US Classification:

371 41

Abstract:

A decoding system and method is disclosed for a radiotelephone system carrying digital messages. A set of multibit high auto-correlation, low cross-correlation synchronization words and their ones complement inverses are employed for message synchronization and supervisory functions. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is substituted. This selected sequence of binary levels is decoded and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated. If the Hamming distance calculated yields a number less than or equal to a number equal to the synchronization error correction capability of the coding function, the decoded sequence is accepted as correct. If the Hamming distance calculation yields a number greater than the error correction capability value, a new set of substituted binary levels is tried.