Stephen Boheng Li

US Patent:

7512148, Mar 31, 2009

Filed:

Dec 9, 2003

Appl. No.:

10/731810

Inventors:

Stephen Li - Plano TX, US
Brian Tse Deng - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04J 3/02

US Classification:

370462, 370412, 370415, 370417

Abstract:

A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue. An output of the second multiplexer is coupled to a control input of the first multiplexer so that the first table entry value is output from the first multiplexer if the corresponding queue has data to be sent out and the second table entry value is sent out from the first multiplexer if the queue corresponding to that table entry has data to be sent out and the queue corresponding to the first entry has no data to be sent out.

US Patent:

20050125590, Jun 9, 2005

Filed:

Dec 9, 2003

Appl. No.:

10/731743

Inventors:

Stephen Li - Plano TX, US
Brian Deng - Richardson TX, US
Paul Howard - Richardson TX, US
Dave Kimble - Carrollton TX, US

International Classification:

G06F013/00

US Classification:

710317000

Abstract:

A PCI Express switch utilizes a central crossbar memory for all ports of the switch. The crossbar memory retains the packet that is to be sent out and only the head pointer for the packet is transmitted to the transmission port. The crossbar memory can also be used as the replay memory for the switch. A circuit for choosing the head pointer at a port for the packet to be sent out, is also disclosed.

US Patent:

20080222370, Sep 11, 2008

Filed:

Mar 10, 2008

Appl. No.:

12/045267

Inventors:

Fitzgerald J Archibald - Bangalore, IN
Stephen Hsiao-Yi Li - Plano TX, US
Michael O. Polley - Garland TX, US
Mohamed F. Mansour - Richardson TX, US
Ramesh Naidu G - Anantapur, IN

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

A method and apparatus of managing data stream, the method comprising archiving received data in a circular buffer; utilizing a breakpoint in realizing the archived received data continuity, wherein the breakpoint is set to the last data portion of the archived received data; when the archiving of the received data approaches the end of the circular buffer, stitching the last portion of the archived received data to the start of the circular buffer; and setting the breakpoint to the updated last data portion of the archived data.

US Patent:

20110271076, Nov 3, 2011

Filed:

Apr 28, 2010

Appl. No.:

12/769080

Inventors:

Maarten Koning - Bloomfield, CA
Stephen Li - Menlo Park CA, US

International Classification:

G06F 15/80
G06F 9/46

US Classification:

712 20, 718100

Abstract:

An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks.

US Patent:

56318480, May 20, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/486487

Inventors:

Frank L. Laczko - Allen TX
Gerard Benbassat - St. Paul de Vence, FR
Stephen H. Li - Garland TX

Assignee:

Texas Instruments - Dallas TX

International Classification:

G06F 1900

US Classification:

364514R

Abstract:

A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

US Patent:

56424370, Jun 24, 1997

Filed:

Apr 26, 1993

Appl. No.:

8/054126

Inventors:

Frank L. Laczko - Allen TX
Gerard Benbassat - St. Paul de Vence, FR
Stephen H. Li - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 740

US Classification:

382246

Abstract:

A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

US Patent:

57941815, Aug 11, 1998

Filed:

Mar 24, 1997

Appl. No.:

8/824072

Inventors:

Gerard Benbassat - St. Paul de Vence, FR
Frank L. Laczko - Allen TX
Stephen H. Li - Garland TX
Kenneth R. Cyr - Carrollton TX
Jonathan L. Rowlands - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G10L 302
G10L 900

US Classification:

704212

Abstract:

A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

US Patent:

48520837, Jul 25, 1989

Filed:

Jun 22, 1987

Appl. No.:

7/065231

Inventors:

Jeffrey A. Niehaus - Dallas TX
Robert G. Fleck - Dallas TX
Stephen Li - Garland TX
Bob D. Strong - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04M 318

US Classification:

370 58

Abstract:

A digital crossbar switch for switching data from an input/output data bus to an internal data bus and to the same or another input/output data bus which includes a plurality of multiplexer logic units, an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer, and a plurality of n-bit input/output data buses one connected to each of the multiplexer logic units were n is an integer. The switch further includes an m/n to 1 multiplexer, where m/n is an integer, in each multiplexer logic unit. The m/n to 1 multiplexer has an input control to the internal data bus and an output coupled to a corresponding one of the input/output data buses and is operative in response to a configuration control signal to switch a selected n-bits of data from the internal data bus to the corresponding input/output data bus. A memory storage for storing configuration control signals is coupled to the m/n to 1 multiplexer.