Stephen J Mann

US Patent:

7765418, Jul 27, 2010

Filed:

Mar 15, 2007

Appl. No.:

11/686450

Inventors:

Stephen Mann - Durham NC, US
Robert Ross - Raleigh NC, US
Iman Taha - Cary NC, US

Assignee:

Qimonda North America Corp. - Durham NC

International Classification:

H04B 1/38

US Classification:

713320, 713340, 375219, 375226, 375356, 375376

Abstract:

A supply voltage is provided in an integrated circuit by retrieving an indicator from a storage device and generating a supply voltage for use by the integrated circuit, the supply voltage being regulated responsive to the indicator being in a first state and unregulated responsive to the indicator being in a second state. Alternatively or additionally, an external voltage provided to the integrated circuit is compared with a threshold. The supply voltage is regulated responsive to the external voltage exceeding the threshold level and unregulated responsive to the external voltage falling below the threshold level.

US Patent:

20080184083, Jul 31, 2008

Filed:

Jan 30, 2007

Appl. No.:

11/668791

Inventors:

Melvin Isom - Durham NC, US
Stephen Mann - Durham NC, US

Assignee:

QIMONDA NORTH AMERICA CORP. - Cary NC

International Classification:

G01R 31/3181
G06F 11/26

US Classification:

714726, 714E11159

Abstract:

A semiconductor integrated circuit device having a physical damage testing capability and a method for testing for physical damage caused during fabrication, assembly or test of the semiconductor integrated circuit are provided. A dedicated conductive test path is formed during fabrication of the integrated circuit device. The test path is routed to pass through areas of the integrated circuit which are susceptible to physical damage. A test circuit is included in the integrated circuit and is connected to the dedicated conductive test path. The test circuit tests the dedicated conductive test path for a characteristic indicative of physical damage. In one embodiment, the test circuit is a continuity circuit that measures whether there is continuity on the conductive test path. The continuity test circuit is activated in response to an externally supplied test command, such as from a test system, and to supply an output signal to a pad that is externally readable by the test system.

US Patent:

58386068, Nov 17, 1998

Filed:

Apr 28, 1997

Appl. No.:

8/845840

Inventors:

Dennis Blankenship - Durham NC
Stephen Mann - Durham NC

Assignee:

Mitsubishi Semiconductor America, Inc. - Durham NC

International Classification:

G11C 1100

US Classification:

365156

Abstract:

A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.