Stephen B Peters

US Patent:

6463554, Oct 8, 2002

Filed:

Sep 17, 1998

Appl. No.:

09/156179

Inventors:

Gerald A Budelman - Portland OR
William A. Hobbs - Beaverton OR
Stephen J. Peters - Aloha OR
Tsvika Kurts - Haifa, IL
Nitin V. Sarangdhar - Portland OR
Kenneth B. Oliver - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 47, 714 43

Abstract:

An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

US Patent:

55133380, Apr 30, 1996

Filed:

Mar 12, 1993

Appl. No.:

8/030801

Inventors:

James W. Alexander - Hillsboro OR
Terri A. Danowski - Aloha OR
Stephen J. Peters - Aloha OR
Ronald J. Whitsel - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100
G06F 1300

US Classification:

395500

Abstract:

An in-circuit emulator trace bus clocking mechanism. A synchronization clock associated with the trace bus is provided. Arrival of a first event on a microprocessor bus to be traced is signified by a transition of a control line. A start of cycle event is detected. A start of cycle signal is generated with respect to the start of cycle event. A two stage pipeline having stage 1 storage elements and stage 2 storage elements are connected to receive data from the microprocessor bus. The start of cycle signal is used to sample data from the microprocessor bus into the stage 1 storage elements. An end of cycle event is detected. An end of cycle signal is generated with reference to the end of cycle event. The end of cycle signal is used to sample data from the stage 1 storage elements into the stage 2 storage elements. The end of cycle signal is also used to sample data appearing on the microprocessor bus at the end of the cycle into the stage 2 storage elements.

US Patent:

58190279, Oct 6, 1998

Filed:

Feb 28, 1996

Appl. No.:

8/607943

Inventors:

Gerald A. Budelman - Portland OR
William A. Hobbs - Beaverton OR
Stephen J. Peters - Aloha OR
Tsvika Kurts - Haifa, IL
Nitin V. Sarangdhar - Portland OR
Kenneth B. Oliver - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

39518401

Abstract:

An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

US Patent:

20140281763, Sep 18, 2014

Filed:

Mar 15, 2013

Appl. No.:

13/842320

Inventors:

Adee O. Ran - Maayan Baruch, IL
Amir Mezer - Haifa, IL
Ophir Gazinski - Ramat Yishai, IL
Sanjay R. Ravi - Hillsboro OR, US
David G. Ellis - Tualatin OR, US
Stephen J. Peters - Aloha OR, US
Jeffrey M. Shuey - Irmo SC, US

International Classification:

G06F 11/07

US Classification:

714704

Abstract:

A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.