Stephen M Prather

age ~54

from Austin, TX

Also known as:
  • Stephen Myles Prather
  • Stephen Stephen Parther
  • Steve Prather
  • Myles Prather
  • Prather Stephen
Phone and address:
5212 Mcdade Dr, Austin, TX 78735
5126944381

Stephen Prather Phones & Addresses

  • 5212 Mcdade Dr, Austin, TX 78735 • 5126944381
  • 9617 Great Hills Trl, Austin, TX 78759 • 5124189004
  • Springfield, LA
  • 1525 Lake Calais Ct, Baton Rouge, LA 70808 • 2257697675
  • Starkville, MS
  • Greenwell Springs, LA
  • Travis, TX

Isbn (Books And Publications)

The New Health Partners: Renewing the Leadership of Physician Practice

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Author
Stephen E. Prather

ISBN #
0787940240

Medical Risk Management

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Author
Stephen E. Prather

ISBN #
0874895812

Us Patents

  • Method And Apparatus For Differential Signal Detection

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  • US Patent:
    6781465, Aug 24, 2004
  • Filed:
    Dec 13, 2002
  • Appl. No.:
    10/318543
  • Inventors:
    Matthew S. Berzins - Austin TX
    Charles A. Cornell - Austin TX
    Stephen M. Prather - Austin TX
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03F 345
  • US Classification:
    330258, 330 69
  • Abstract:
    Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.
  • Method And Circuit For Translating A Differential Signal To Complementary Cmos Levels

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  • US Patent:
    7173453, Feb 6, 2007
  • Filed:
    Dec 17, 2004
  • Appl. No.:
    11/015059
  • Inventors:
    Stephen M. Prather - Austin TX, US
    Matthew S. Berzins - Cedar Park TX, US
    Jeffrey W. Waldrip - Austin TX, US
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03K 19/0175
  • US Classification:
    326 80, 326 81, 326 63, 326 68
  • Abstract:
    A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.
  • Low Duty Cycle Distortion Differential To Cmos Translator

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  • US Patent:
    7176720, Feb 13, 2007
  • Filed:
    Mar 11, 2004
  • Appl. No.:
    10/798657
  • Inventors:
    Stephen M. Prather - Austin TX, US
    Jeffrey F. Waldrip - Austin TX, US
    Matthew S. Berzins - Austin TX, US
    Charles A. Cornell - Austin TX, US
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03K 19/0175
    H03K 3/45
  • US Classification:
    326 80, 326 81, 330261
  • Abstract:
    Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.
  • Circuit And Method For Cmos Voltage Level Translation

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  • US Patent:
    7239178, Jul 3, 2007
  • Filed:
    Mar 23, 2005
  • Appl. No.:
    11/090935
  • Inventors:
    Charles A. Cornell - Austin TX, US
    Matthew S. Berzins - Cedar Park TX, US
    Stephen M. Prather - Austin TX, US
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03K 19/0175
  • US Classification:
    326 81, 326 68
  • Abstract:
    A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.
  • Circuit And Method For Rapid Power Up Of A Differential Output Driver

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  • US Patent:
    7394293, Jul 1, 2008
  • Filed:
    Nov 23, 2005
  • Appl. No.:
    11/286764
  • Inventors:
    Jeffrey Waldrip - Austin TX, US
    Stephen M. Prather - Austin TX, US
    Matthew Berzins - Austin TX, US
    Charles Cornell - Austin TX, US
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03K 19/0175
  • US Classification:
    326 83, 326 81, 326 68
  • Abstract:
    Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.
  • Linearized Digital Phase-Locked Loop Method For Maintaining End Of Packet Time Linearity

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  • US Patent:
    7826581, Nov 2, 2010
  • Filed:
    Oct 5, 2004
  • Appl. No.:
    10/959259
  • Inventors:
    Stephen M. Prather - Austin TX, US
    Matthew S. Berzins - Austin TX, US
    Charles A. Cornell - Austin TX, US
    Steven P. Larky - Del Mar CA, US
    Joseph A. Cetin - San Diego CA, US
  • Assignee:
    Cypress Semiconductor Corporation - San Jose CA
  • International Classification:
    H03D 3/24
  • US Classification:
    375373, 375376
  • Abstract:
    An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.
  • Control Signal Generator For An Overvoltage-Tolerant Interface Circuit On A Low Voltage Process

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  • US Patent:
    6496054, Dec 17, 2002
  • Filed:
    May 9, 2001
  • Appl. No.:
    09/852185
  • Inventors:
    Stephen Myles Prather - Austin TX
    Jeffrey William Waldrip - Austin TX
  • Assignee:
    Cypress Semiconductor Corp. - San Jose CA
  • International Classification:
    H03K 301
  • US Classification:
    327534
  • Abstract:
    A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.

Medicine Doctors

Stephen Prather Photo 1

Stephen E Prather

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Specialties:
Obstetrics & Gynecology

Classmates

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Stephen Prather | Metamor...

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Stephen Prather Photo 3

Steve Prather, North Cobb...

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Stephen Prather Photo 4

Steve Prather, Leland Hig...

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Stephen Prather Photo 5

Washington Elementary Sch...

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Graduates:
Debbie Stein (1955-1963),
Vickie Burrell (1962-1967),
Tom Taylor (1952-1954),
Patti Crockett (1974-1975),
Steve Prather (1950-1955)
Stephen Prather Photo 6

Holy Angels High School, ...

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Graduates:
Steve Prather (1959-1963),
Kathryn Houldsworth (1952-1956),
Thomas Anthony (1958-1962),
Sue Becker (1953-1957)
Stephen Prather Photo 7

Metamora Township High Sc...

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Graduates:
Stephen Prather (1980-1984),
Kaleb Rhoads (2003-2007),
Julie Brousset (1978-1982),
Amy Bishop (1985-1989)
Stephen Prather Photo 8

Pekin Community High Scho...

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Graduates:
Steve Prather (1970-1974),
Staci Fisher Turner (1981-1985),
Julie Barwick (1972-1976),
Charlie Farley (1976-1980)
Stephen Prather Photo 9

Awtrey Middle School, Ken...

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Graduates:
Steve Prather (1973-1975),
Emily Hambrick (1989-1991),
James Mills (1973-1975),
Jimmy Daniel (1965-1967),
Tyler Dobson (1983-1986),
Scott Jones (1976-1978)

Youtube

Episode 13: Stephen Prather - SportSource Ana...

Episode 13 of the Process, Preparation and Performance Podcast is our ...

  • Duration:
    1h 27m 43s

Jeffersonville High School Marching Band - St...

Produced 5-23-2008.

  • Duration:
    4m 16s

The Stephen Prather Chronicles

Stephen Prather Audition tape Produced 5-23-2008.

  • Duration:
    4m 13s

Stephen Prather review of Killing Jesus

  • Duration:
    1m 49s

Jeff High Percussion Ansemble Story - Stephen...

  • Duration:
    3m 15s

This is a Library - Blonde Logic PSA - Stephe...

Produced 12-18-2007.

  • Duration:
    32s

Flickr

Plaxo

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Stephen Prather

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Vice President - Brokerage at Chas Hawkins Co Inc...

Facebook

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Stephen Prather

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Stephen Prather Photo 15

Stephen Prather

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Stephen Prather Photo 16

Stephen Prather Jr

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Stephen Prather Photo 17

Stephen Prather

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Stephen Prather Photo 18

Stephen Prather

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Stephen Prather Photo 19

Stephen Prather

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Stephen Prather Photo 20

Stephen Prather

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Stephen Prather Photo 21

Stephen Prather

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Myspace

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Stephen Prather

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Locality:
VIRGINIA, Illinois
Gender:
Male
Birthday:
1949
Stephen Prather Photo 23

stephen prather

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Locality:
WASHBURN, Illinois
Gender:
Male
Birthday:
1918
Stephen Prather Photo 24

Stephen Prather

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Gender:
Male
Birthday:
1949
Stephen Prather Photo 25

Stephen Prather Cain

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Gender:
Male
Birthday:
1945

Googleplus

Stephen Prather Photo 26

Stephen Prather

Lived:
Austin, tx
Manassas, va
Springfield, la
Baton rouge, la
Metairie, la
Work:
Synopsys - Applications Consultant (2005)
Cypress Semiconductor - Analog Circuit Designer (1997-2005)
Louisiana State University - Teaching Assistant (1995-1997)
Education:
Louisiana State University - Electrical Engineering, Springfield High School, LSU
About:
Got it all figured out.
Tagline:
May Google+ deliver us from FB evil
Bragging Rights:
Cured cancer.
Stephen Prather Photo 27

Stephen Prather


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