Matthew S. Berzins - Austin TX Charles A. Cornell - Austin TX Stephen M. Prather - Austin TX
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03F 345
US Classification:
330258, 330 69
Abstract:
Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.
Method And Circuit For Translating A Differential Signal To Complementary Cmos Levels
Stephen M. Prather - Austin TX, US Matthew S. Berzins - Cedar Park TX, US Jeffrey W. Waldrip - Austin TX, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 19/0175
US Classification:
326 80, 326 81, 326 63, 326 68
Abstract:
A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.
Low Duty Cycle Distortion Differential To Cmos Translator
Stephen M. Prather - Austin TX, US Jeffrey F. Waldrip - Austin TX, US Matthew S. Berzins - Austin TX, US Charles A. Cornell - Austin TX, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 19/0175 H03K 3/45
US Classification:
326 80, 326 81, 330261
Abstract:
Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.
Circuit And Method For Cmos Voltage Level Translation
Charles A. Cornell - Austin TX, US Matthew S. Berzins - Cedar Park TX, US Stephen M. Prather - Austin TX, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 19/0175
US Classification:
326 81, 326 68
Abstract:
A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.
Circuit And Method For Rapid Power Up Of A Differential Output Driver
Jeffrey Waldrip - Austin TX, US Stephen M. Prather - Austin TX, US Matthew Berzins - Austin TX, US Charles Cornell - Austin TX, US
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 19/0175
US Classification:
326 83, 326 81, 326 68
Abstract:
Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.
Linearized Digital Phase-Locked Loop Method For Maintaining End Of Packet Time Linearity
Stephen M. Prather - Austin TX, US Matthew S. Berzins - Austin TX, US Charles A. Cornell - Austin TX, US Steven P. Larky - Del Mar CA, US Joseph A. Cetin - San Diego CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03D 3/24
US Classification:
375373, 375376
Abstract:
An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.
Control Signal Generator For An Overvoltage-Tolerant Interface Circuit On A Low Voltage Process
Stephen Myles Prather - Austin TX Jeffrey William Waldrip - Austin TX
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 301
US Classification:
327534
Abstract:
A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.
Steve Prather (1973-1975), Emily Hambrick (1989-1991), James Mills (1973-1975), Jimmy Daniel (1965-1967), Tyler Dobson (1983-1986), Scott Jones (1976-1978)
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