Stephen E Rich

US Patent:

20130340034, Dec 19, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/995972

Inventors:

Stephen E. Rich - Portland OR, US
Gyan Prakash - Beaverton OR, US
James F. Bodio - Tigard OR, US
Selim Aissi - Beaverton OR, US

International Classification:

H04L 29/06

US Classification:

726 1

Abstract:

In one embodiment, the present invention includes a method for launching an application authentication policy (AAP) application on a computing device, enabling the device for use as a personal device of a user if the user is authenticated by the AAP application, and otherwise enabling the device for use as a non-personal device that provides only basic functionality but protects other users' personal data and applications. Other embodiments are described and claimed.

US Patent:

56405260, Jun 17, 1997

Filed:

Dec 21, 1994

Appl. No.:

8/360520

Inventors:

Stephen William Mahin - Underhill VT
Stephen Michael Conor - Essex Junction VT
Stephen J. Ciavaglia - Williston VT
Lyman Henry Moulton - Phoenix AZ
Stephen Emery Rich - Essex Junction VT
Paul David Kartschoke - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9312

US Classification:

395383

Abstract:

A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i. e. , store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.

US Patent:

56257872, Apr 29, 1997

Filed:

May 12, 1995

Appl. No.:

8/440034

Inventors:

Stephen W. Mahin - Underhill VT
Stephen M. Conor - Essex Junction VT
Stephen J. Ciavaglia - Williston VT
Lyman H. Moulton - Phoenix AZ
Stephen E. Rich - Essex Junction VT
Paul D. Kartschoke - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

395380

Abstract:

A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i. e. , store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.

US Patent:

56447442, Jul 1, 1997

Filed:

May 12, 1995

Appl. No.:

8/440035

Inventors:

Stephen William Mahin - Underhill VT
Stephen Michael Conor - Essex Junction VT
Stephen J. Ciavaglia - Williston VT
Lyman Henry Moulton - Phoenix AZ
Stephen Emery Rich - Essex Junction VT
Paul David Kartschoke - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9312

US Classification:

395383

Abstract:

A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i. e. , store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.

US Patent:

20160188284, Jun 30, 2016

Filed:

Dec 26, 2014

Appl. No.:

14/583264

Inventors:

- Santa Clara CA, US
Jonathan J. Huang - Pleasanton CA, US
Stephen E. Rich - Portland OR, US
Noah Fishel - Portland OR, US

International Classification:

G06F 3/16
H04R 1/10

Abstract:

Systems and methods may provide for determining a usage context of a headset and detecting one or more danger-related conditions based on the usage context. Additionally, one or more settings of the headset may be adjusted in response to at least one of the one or more danger-related conditions. In one example, adjusting the one or more settings includes one or more of deactivating noise cancellation, adjusting noise cancellation to increase an intensity of at least one of the one or more danger-related sounds, or adjusting one or more audio playback settings associated with the headset.