Stephen P Robb

US Patent:

6504424, Jan 7, 2003

Filed:

Aug 29, 2001

Appl. No.:

09/942053

Inventors:

David M. Heminger - Mesa AZ
Stephen P. Robb - Tempe AZ
Margaret E. Fuchs - Mesa AZ

Assignee:

Semiconductor Components Industries LLC - Phoenix AZ

International Classification:

H01L 2500

US Classification:

327566, 327312

Abstract:

Depletion mode pass transistor ( ) accepts input voltage V and provides regulated output voltage V. The regulated output voltage is referenced to the threshold voltage of MOSFET ( ) and is directly proportional to the ratio of resistors ( and ). MOSFET ( ) provides enabling and disabling of voltage regulator ( ). Multiple voltage regulators (FIG. ) having multiple output potentials are realized on the same semiconductor die producing the same threshold potential for MOSFETs ( ), whereby the output potentials are selectable using the ratio of resistors and. Constant current source ( ) reduces output voltage variation due to input voltage variation.

US Patent:

6507070, Jan 14, 2003

Filed:

Nov 25, 1996

Appl. No.:

08/755926

Inventors:

Zheng Shen - Chandler AZ
Stephen P. Robb - Tempe AZ
Chang Su Mitter - Tempe AZ

Assignee:

Semiconductor Components Industries LLC - Phoenix AZ

International Classification:

H01L 2976

US Classification:

257341, 257344

Abstract:

A semiconductor device ( ) is formed that is bi-lateral and has a voltage blocking capability that is well suited to applications involving portable electronics. The semiconductor device has an epitaxial layer ( ) that is formed on a semiconductor substrate ( ). A doped region ( ) is formed that extends from a top surface ( ) of the epitaxial layer ( ) to the underlying semiconductor substrate ( ). The semiconductor device ( ) has a source region ( ) that is separated from the doped region ( ) to provide a channel region ( ). The channel region ( ) is modulated by a gate structure ( ) to determine if a current flow should be allowed through semiconductor device ( ) or if semiconductor device ( ) is to provide voltage blocking capability.

US Patent:

6633063, Oct 14, 2003

Filed:

May 4, 2001

Appl. No.:

09/849720

Inventors:

Francine Y. Robb - Tempe AZ
Jeffrey Pearse - Chandler AZ
David M. Heminger - Mesa AZ
Stephen P. Robb - Tempe AZ

Assignee:

Semiconductor Components Industries LLC - Phoenix AZ

International Classification:

H01L 2976

US Classification:

257332, 257288, 257263, 257328, 257329, 257330

Abstract:

A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0. 5 and 5 volts. Trench MOS based TVS device ( ) provides an enhanced gain operation, while device ( ) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

US Patent:

6781502, Aug 24, 2004

Filed:

May 6, 2003

Appl. No.:

10/429399

Inventors:

Stephen P. Robb - Fountain Hills AZ

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

H01H 85044

US Classification:

337167, 337206, 337221, 361 54, 361 931, 361 937, 361101

Abstract:

A protection circuit ( ) is formed to protected a load ( ) when a short circuit develops during operation of the load ( ). A load transistor ( ) is formed to couple the load to a voltage return terminal. A disable transistor ( ) is formed to disable the load transistor ( ) when a short circuit occurs.

US Patent:

6841437, Jan 11, 2005

Filed:

Jun 20, 2003

Appl. No.:

10/464971

Inventors:

Stephen P. Robb - Fountain Hills AZ, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

H01L 218238
H01L 21336

US Classification:

438209, 438206, 438208, 438268

Abstract:

A method of forming medium breakdown voltage vertical transistors () and lateral transistors () on the same substrate () provides for optimizing the epitaxial layer () for the lateral transistors (). The vertical transistor () is formed in a well () that has a lower resistivity than the epitaxial layer () to provide the required low on-resistance for the vertical power transistor ().

US Patent:

6949961, Sep 27, 2005

Filed:

Oct 6, 2003

Appl. No.:

10/678769

Inventors:

Stephen P. Robb - Fountain Hills AZ, US
David K. Briggs - Glendale AZ, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

H01L029/94
H01L031/062
H01L031/113
H01L031/119

US Classification:

327 52, 327 54, 327 56, 327 87, 257341

Abstract:

In one embodiment, a power switch device () includes a first MOSFET device and a second MOSFET device (). A split gate structure () including a first gate electrode () controls the first MOSFET device (). A second gate electrode () controls the second MOSFET device (). A current limit device () is coupled to the first gate electrode () to turn on the first MOSFET device during a current limit mode. A comparator device () is coupled to the second gate electrode () to turn on the second MOSFET device () when the power switch device () is no longer in current limit mode.

US Patent:

7030447, Apr 18, 2006

Filed:

Jul 15, 2003

Appl. No.:

10/620259

Inventors:

Francine Y. Robb - Fountain Hills AZ, US
Jeffrey Pearse - Chandler AZ, US
David M. Heminger - Mesa AZ, US
Stephen P. Robb - Fountain Hills AZ, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

H01L 23/62

US Classification:

257361, 257360, 257362

Abstract:

A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0. 5 and 5 volts. Trench MOS based TVS device () provides an enhanced gain operation, while device () provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

US Patent:

7099135, Aug 29, 2006

Filed:

Nov 5, 2002

Appl. No.:

10/287831

Inventors:

Alan Ball - Gilbert AZ, US
David Briggs - Glendale AZ, US
Suzanne Nee - Gilbert AZ, US
Stephen Robb - Fountain Hills AZ, US

Assignee:

Semiconductor Components Industries, L.L.C - Phoenix AZ

International Classification:

H02H 3/00

US Classification:

361 939, 361 58

Abstract:

An inrush current limiter circuit () includes a detection circuit () that produces a control signal (V) from a sense current (I). A power transistor responds to the control signal and has a source () coupled to an input node () to receive a supply voltage (ground) and a drain () for routing a load current (I) to an output node () as a protection signal (V). A sense transistor responds to the control signal and has a source scaled to the source of the power transistor and coupled to the input node to route a portion of the load current to the output node as the sense current.