Stephen G Robinson

US Patent:

20220197822, Jun 23, 2022

Filed:

Dec 23, 2020

Appl. No.:

17/133570

Inventors:

- Santa Clara CA, US
Gilbert NEIGER - Portland OR, US
Stephen ROBINSON - Austin TX, US
Dan BAUM - Haifa, IL
Ron GABOR - Haifa, IL

International Classification:

G06F 12/1027
G06F 11/07

Abstract:

Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit an X-bit address field starting at a bit to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.

US Patent:

20200004959, Jan 2, 2020

Filed:

Jun 28, 2019

Appl. No.:

16/456578

Inventors:

Robert S. Chappell - Portland OR, US
Joseph Nuzman - Haifa, IL
Stephen Robinson - Austin TX, US
Jason W. Brandt - Austin TX, US

International Classification:

G06F 21/55
G06F 21/62
G06F 9/48
G06F 9/30
G06F 12/0802

Abstract:

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

US Patent:

20150277949, Oct 1, 2015

Filed:

Mar 27, 2014

Appl. No.:

14/227166

Inventors:

THIAM WAH LOH - Singapore, SG
GAUTHAM N. CHINYA - Hillsboro OR, US
STEPHEN J. ROBINSON - Austin TX, US
REZA FORTAS - Villeneuve Loubet, FR
HONG WANG - Santa Clara CA, US
HELMUT REINIG - Isen, DE
PER HAMMARLUND - Hillsboro OR, US
DEEPAK A. MATHAIKUTTY - Santa Clara CA, US
CHRISTIAN ERBEN - Munich, DE

International Classification:

G06F 9/455
G06F 13/16
G06F 13/364
G06F 12/14

Abstract:

A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.

US Patent:

20150278119, Oct 1, 2015

Filed:

Mar 27, 2014

Appl. No.:

14/227178

Inventors:

THIAM WAH LOH - Singapore, SG
PER HAMMARLUND - Hillsboro OR, US
ANDREAS WASSERBAUER - Pettenbach, AT
SWEE CHONG PETER KUAN - Singapore, SG
ECKHARD DELFS - Nuremberg, DE
DEEPAK A. MATHAIKUTTY - Santa Clara CA, US
STEPHEN J. ROBINSON - Austin TX, US
GAUTHAM N. CHINYA - Hillsboro OR, US
PERRY H. WANG - San Jose CA, US
CHEE WENG TAN - Singapore, SG
HONG WANG - Santa Clara CA, US
REZA FORTAS - Villeneuve Loubet, FR

International Classification:

G06F 12/14
G11C 29/52
G06F 21/57
G11C 7/10

Abstract:

Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

US Patent:

20140372987, Dec 18, 2014

Filed:

Jun 15, 2013

Appl. No.:

13/918940

Inventors:

Beeman C. Strong - Portland OR, US
Jason W. Brandt - Austin TX, US
Tsvika Kurts - Haifa, IL
Peter Lachner - Heroldstatt, DE
Itamar Kazachinsky - Netanya, IL
Stephen J. Robinson - Austin TX, US
Peggy J. Irelan - Chandler AZ, US

International Classification:

G06F 11/34

US Classification:

717128

Abstract:

A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.