Stephen J Robinson

US Patent:

6859721, Feb 22, 2005

Filed:

Dec 21, 2001

Appl. No.:

10/027270

Inventors:

Shane R. Runquist - Austin TX, US
Stephen C. Robinson - Olathe KS, US
Thomas H. Walters - Gardner KS, US
Mark D. Tompkins - Overland Park KS, US

Assignee:

Garmin Ltd.

International Classification:

G01C021/30
G01S005/02

US Classification:

701200, 701201, 701209, 701211, 34235709, 34235706

Abstract:

Systems, devices and methods are provided to display or otherwise provide addresses in proximity to the device, and to periodically update the addresses as the navigational aid device is transported along a road. The device is adapted to be transported on a road. The device includes a processor and a memory adapted to communicate with the processor. The processor and the memory are adapted to cooperate to provide an address that is proximate to the device. Another aspect includes a method. According to one method embodiment, an address proximate to a navigational aid device is estimated and displayed on the navigational aid device. Other aspects are provided herein.

US Patent:

7079947, Jul 18, 2006

Filed:

Dec 23, 2004

Appl. No.:

11/020288

Inventors:

Shane R. Runquist - Austin TX, US
Stephen C. Robinson - Olathe KS, US
Thomas H. Walters - Gardner KS, US
Mark D. Tompkins - Overland Park KS, US

Assignee:

Garmin Ltd.

International Classification:

G01C 21/30
G01C 21/32

US Classification:

701210, 701207, 701208, 701211, 701213

Abstract:

Systems, devices and methods are provided to display or otherwise provide addresses in proximity to the device, and to periodically update the addresses as the navigational aid device is transported along a road. The device is adapted to be transported on a road. The device includes a processor and a memory adapted to communicate with the processor. The processor and the memory are adapted to cooperate to provide an address that is proximate to the device. Another aspect includes a method. According to one method embodiment, an address proximate to a navigational aid device is estimated and displayed on the navigational aid device. Other aspects are provided herein.

US Patent:

7302108, Nov 27, 2007

Filed:

Feb 4, 2004

Appl. No.:

10/771533

Inventors:

Kevin Lee Hanes - Round Rock TX, US
Kent William Nagase - Cedar Park TX, US
Stephen Haskell Robinson - Belton TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06K 9/40

US Classification:

382254, 382260, 382275, 382303, 358 326, 358 327, 358463, 713154, 713155, 713160

Abstract:

Restore media, such as a CD, for restoring an information handling system to a manufacture state is automatically created from the manufacture image and descriptive files used to create the manufacture load script. A restore media adapter expands the manufacture image to determine the manufacture state partitions, associates identification information metadata with the image, generates restore media load script to install the image on an information handling system with compatible partitions, and formats the image and load script as virtual restore media, such as a virtual CD. The virtual restore media acts as a master for archiving and communicates through electronic communication, such as a network, to a replicator for mass production of restore media.

US Patent:

8533721, Sep 10, 2013

Filed:

Mar 26, 2010

Appl. No.:

12/748203

Inventors:

Stephen J. Robinson - Austin TX, US
Deepak Limaye - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 9/40
G06F 7/38

US Classification:

718103, 718102, 718107, 712220, 712215, 712214, 712237

Abstract:

A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling loop into two consecutive cycles. The scheduling loop includes a compare stage, a ready stage and a pick stage. The compare stage and the ready stage are executed in a first of the two consecutive cycles and the pick stage is executed in a second of the two consecutive cycles. By splitting each scheduling loop into two consecutive cycles, selecting the oldest operation by default and checking the readiness of the oldest operation, it relieves the system of timing requirements and avoids the need for power hungry logic. Every execution of an operation does not appear as one extra cycle longer and the lazy out-of-order scheduler retains most of the performance of a full out-of-order scheduler.

US Patent:

20140068230, Mar 6, 2014

Filed:

Oct 4, 2012

Appl. No.:

13/977064

Inventors:

Venkateswara Madduri - Austin TX, US
Jonathan Combs - Austin TX, US
James E. Phillips - Round Rock TX, US
Stephen J. Robinson - Austin TX, US
James D. Allen - Austin TX, US
Jonathan J. Tyler - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712216

Abstract:

A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

US Patent:

20220405234, Dec 22, 2022

Filed:

May 30, 2022

Appl. No.:

17/827882

Inventors:

- Santa Clara CA, US
Stephen J. Robinson - Austin TX, US
Christopher D. Bryant - Austin TX, US
Jason W. Brandt - Austin TX, US

International Classification:

G06F 15/80
G06F 9/30

Abstract:

A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

US Patent:

20220335126, Oct 20, 2022

Filed:

Feb 1, 2022

Appl. No.:

17/590470

Inventors:

- Santa Clara CA, US
Joseph Nuzman - Haifa, IL
Stephen Robinson - Austin TX, US
Jason W. Brandt - Austin TX, US

International Classification:

G06F 21/55
G06F 21/62
G06F 9/48
G06F 12/0802
G06F 9/30

Abstract:

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

US Patent:

20220309005, Sep 29, 2022

Filed:

Mar 27, 2021

Appl. No.:

17/214851

Inventors:

- Santa Clara CA, US
Krishnakumar GANAPATHY - Bee Cave TX, US
Venkateswara MADDURI - Austin TX, US
James ALLEN - Austin TX, US
James COLEMAN - Mesa AZ, US
Stephen ROBINSON - Austin TX, US

International Classification:

G06F 12/0897
G06F 3/06

Abstract:

Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.