Stephen Wayne Russell

US Patent:

7001848, Feb 21, 2006

Filed:

Nov 25, 1998

Appl. No.:

09/199829

Inventors:

Patricia B. Smith - Grapevine TX, US
David B. Aldrich - Allen TX, US
Stephen W. Russell - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/302

US Classification:

438725, 438710, 438714, 438738

Abstract:

Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer of FIG. ) on the first conductor (conductor of FIG. ), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer of FIG. ) on the dielectric layer, the oxygen-sensitive material substantially filling the opening in the dielectric layer and for providing an electrical contact to the first conductor; forming a photoresist layer on the oxygen-sensitive material, the photoresist layer having a pattern so as to expose portions of the oxygen-sensitive material; removing the exposed portions of the oxygen-sensitive material on the dielectric material, the removal step causing a residue to be formed on exposed surfaces of the remaining portions of the oxygen-sensitive material; and removing the photoresist layer by subjecting the photoresist layer with a hydrogen-containing gas incorporated into a plasma.

US Patent:

62187325, Apr 17, 2001

Filed:

Jul 15, 1999

Appl. No.:

9/354510

Inventors:

Stephen W. Russell - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257748

Abstract:

An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.

US Patent:

61301566, Oct 10, 2000

Filed:

Mar 30, 1999

Appl. No.:

9/281538

Inventors:

Robert H. Havemann - Garland TX
Girish A. Dixit - Plano TX
Stephen W. Russell - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21441

US Classification:

438637

Abstract:

A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.

US Patent:

62517716, Jun 26, 2001

Filed:

Feb 22, 1999

Appl. No.:

9/255466

Inventors:

Patricia B. Smith - Colleyville TX
Girish A. Dixit - Plano TX
Eden Zielinski - Rowlett TX
Stephen W. Russell - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438626

Abstract:

An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step 102 of FIG. 1); forming a layer of the metallic conductor on the dielectric layer (step 104 of FIG. 1); removing a portion of the layer of the metallic conductor on the dielectric layer (step 106 of FIG. 1); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step 110 of FIG. 1). Preferably, the plasma contains a substance selected from the group consisting of: NH. sub. 3, N. sub. 2 H. sub. 2, H. sub. 2 S, and CH. sub. 4, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof.

US Patent:

62710788, Aug 7, 2001

Filed:

Jun 3, 1999

Appl. No.:

9/324949

Inventors:

Stephen W. Russell - Dallas TX
Antonio L. P. Rotondaro - Dallas TX
Donald L. Plumton - Dallas TX
Duane E. Carter - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438241

Abstract:

A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.