Stephen Wayne Spriggs

US Patent:

6414900, Jul 2, 2002

Filed:

Dec 3, 2001

Appl. No.:

09/998824

Inventors:

Stephen W. Spriggs - Rowlett TX
George B. Jamison - Murphy TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800

US Classification:

36523006, 36523008

Abstract:

A memory device ( ) includes a memory array ( ) having storage units ( ) arranged in a plurality of rows ( ). A row decoder ( ) receives address information and determines which of the plurality of rows ( ) to enable. According to the determined row ( ), a row selector ( ) drives the storage units ( ) associated with the determined row ( ) to provide their outputs onto respective bitlines ( ) for identification by a bitline sensor ( ). If the received address information indicates an out of range address that does not identify any of the plurality of rows ( ) of the memory array ( ), an out of range decoder ( ) provides such determination to drive an out of range selector ( ) to enable storage units ( ) arranged in a single row ( ) of a bitline driver ( ). Outputs from the storage units ( ) are applied to the respective bitlines ( ) during an out of range address occurrence to prevent the bitlines ( ) from being placed in an undesirable floating state.

US Patent:

6799134, Sep 28, 2004

Filed:

Aug 9, 2002

Appl. No.:

10/216455

Inventors:

Brian D. Borchers - Wylie TX
Stephen W. Spriggs - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1900

US Classification:

702125, 710 5

Abstract:

A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit in burst mode by detecting and measuring an output of the self-timed sequential circuit.

US Patent:

6956789, Oct 18, 2005

Filed:

Sep 16, 2003

Appl. No.:

10/663575

Inventors:

Vikas K. Agrawal - Dallas TX, US
Bryan D. Sheffield - Rowlett TX, US
Stephen W. Spriggs - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C008/00

US Classification:

3652335, 365193, 365194, 365202, 365203, 365233, 365241

Abstract:

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

US Patent:

7012846, Mar 14, 2006

Filed:

Feb 2, 2004

Appl. No.:

10/768098

Inventors:

Suresh Balasubramanian - Coimbatore TamilNadu, IN
Stephen Wayne Spriggs - Rowlett TX, US
Bryan D. Sheffield - Rowlett TX, US
Mohan Mishra - Madhubani, IN

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

365205, 365208, 365242, 365243, 36518905

Abstract:

A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.

US Patent:

7016245, Mar 21, 2006

Filed:

Feb 2, 2004

Appl. No.:

10/768131

Inventors:

Suresh Balasubramanian - Coimbatore, IN
Stephen Wayne Spriggs - Rowlett TX, US
Bryan D. Sheffield - Rowlett TX, US
Mohan Mishra - Madhubani, IN

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/02

US Classification:

365207, 365205, 36518905, 365194

Abstract:

An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.

US Patent:

7042030, May 9, 2006

Filed:

Nov 21, 2003

Appl. No.:

10/717551

Inventors:

Suresh Balasuramanian - Coimbatore, IN
Stephen Wayne Spriggs - Rowlett TX, US
George Jamison - Murphy TX, US
Mohan Mishra - Madhubani, IN

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/10

US Classification:

257211, 257208

Abstract:

The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

US Patent:

7200730, Apr 3, 2007

Filed:

Sep 16, 2003

Appl. No.:

10/663144

Inventors:

Bryan D. Sheffield - Rowlett TX, US
Vikas K. Agrawal - Dallas TX, US
Stephen W. Spriggs - Rowlett TX, US
Eric L. Badi - Cagnes sur Mer, FR

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 13/00

US Classification:

711167, 711105, 710 58, 710 61, 712220, 712227, 713400, 36518901, 365191, 365193

Abstract:

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

US Patent:

7210078, Apr 24, 2007

Filed:

Aug 29, 2002

Appl. No.:

10/230543

Inventors:

Brian D. Borchers - Wylie TX, US
Stephen W. Spriggs - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 29/00
G01R 31/28
G06F 11/00

US Classification:

714718, 714724, 714 37, 265201

Abstract:

A method for evaluating an output of a sequential circuit by storing a series of output pulses from the sequential circuit and determining whether the output pulses toggled as desired. Also a circuit for evaluating an output of a sequential circuit that determines if the output pulses toggled as desired.