Stephen T. Trinh - San Jose CA, US Dixie H. Nguyen - San Jose CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 29/00
US Classification:
365200, 365 49
Abstract:
A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The content addressable memory decodes the address and produces column redundancy information as an output. The column redundancy information is latched during a period complementary to the memory access cycle. By utilizing complementary memory access phases to latch memory addresses in contrast with a utilization of column redundancy information, a single set of registers may be used. Additionally, concurrent read and write operations are supported.
Channel Discharging After Erasing Flash Memory Devices
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
Column Redundancy Ram For Dynamic Bit Replacement In Flash Memory
Alan Chen - Saratoga CA, US Neville Ichhaporia - San Jose CA, US Vijay P. Adusumilli - San Jose CA, US Stephen Trinh - San Jose CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G11C 16/06 G11C 16/04
US Classification:
36518509, 36518533
Abstract:
A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
Channel Discharging After Erasing Flash Memory Devices
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
Adaptive Programming For Non-Volatile Memory Devices
Danut Manea - Saratoga CA, US Erwin Castillon - Milpitas CA, US Uday Mudumba - San Jose CA, US Sabina Centazzo - Sunnyvale CA, US Stephen Trinh - San Jose CA, US Dixie Nguyen - San Jose CA, US
Assignee:
ATMEL CORPORATION - San Jose CA
International Classification:
G11C 16/10
US Classification:
36518518
Abstract:
Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.
Richard V. De Caro - El Dorado Hills CA, US Danut Manea - Saratoga CA, US YONGLIANG WANG - Saratoga CA, US Stephen Trinh - San Jose CA, US Paul Hill - Southampton, GB
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 1/32
US Classification:
713324
Abstract:
A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
Column/Sector Redundancy Cam Fast Programming Scheme Using Regular Memory Core Array In Multi-Plane Flash Memory Device
Programming redundant columns for a multi-plane EEPROM includes identifying a defective memory column during a back-end testing operation to provide redundancy information in the form of the original address for the defective column and the address for corresponding fuse links that are programmed to access a redundant column instead of the defective column. From the address for the corresponding fuse links are provided redundant column word-line select (COL RED WL Select) signals to WL input terminals of a Column Redundancy CAM. From the address for the corresponding fuse links are provided column address decoded COL Address Decoded signals to decoded column address input terminals of the Column Redundancy CAM. All of the fuse links are simultaneously programmed.
Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
- San Jose CA, US Thuan Vu - San Jose CA, US Stephen Trinh - San Jose CA, US Stanley Hong - San Jose CA, US Anh Ly - San Jose CA, US Steven Lemke - Boulder Creek CA, US Nha Nguyen - San Jose CA, US Vipin Tiwari - Dublin CA, US Nhan Do - Saratoga CA, US
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.