Steve E Cole

US Patent:

7205584, Apr 17, 2007

Filed:

Dec 22, 2003

Appl. No.:

10/740599

Inventors:

Howard E. Rhodes - Boise ID, US
Steve Cole - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 31/0328

US Classification:

257184, 257187, 257291, 257292, 257461, 257462

Abstract:

A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

US Patent:

7462534, Dec 9, 2008

Filed:

Aug 2, 2005

Appl. No.:

11/196051

Inventors:

Kunal R. Parekh - Boise ID, US
Suraj Mathew - Boise ID, US
Steve Cole - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/8244

US Classification:

438241, 438300, 257E21209

Abstract:

The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

US Patent:

7713809, May 11, 2010

Filed:

Oct 13, 2006

Appl. No.:

11/580013

Inventors:

Howard E. Rhodes - Boise ID, US
Steve Cole - Boise ID, US

Assignee:

Aptina Imaging Corporation - Grand Cayman

International Classification:

H01L 21/8238

US Classification:

438223, 438231, 438248, 438294, 438423, 257E2154

Abstract:

A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

US Patent:

7919828, Apr 5, 2011

Filed:

Oct 13, 2006

Appl. No.:

11/580012

Inventors:

Howard E. Rhodes - Boise ID, US
Steve Cole - Boise ID, US

Assignee:

Aptina Imaging Corporation - George Town

International Classification:

H01L 29/00

US Classification:

257506, 257510, 257 72, 257 59

Abstract:

A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

US Patent:

53468368, Sep 13, 1994

Filed:

Aug 17, 1993

Appl. No.:

8/108147

Inventors:

Monte Manning - Kuna ID
Steve V. Cole - Boise ID
Tyler A. Lowrey - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21283
H01L 21223

US Classification:

437 46

Abstract:

A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper level polysilicon interconnect. The doping technique combines a doping implant of the upper level polysilicon and an ion-mixing implant into a single implant thereby achieving a low resistive implant which also reduces processing steps.

US Patent:

20210028308, Jan 28, 2021

Filed:

Jul 25, 2019

Appl. No.:

16/522390

Inventors:

- Boise ID, US
Steve V. Cole - Boise ID, US
Scott J. Derner - Boise ID, US
Toby D. Robbs - Boise ID, US

International Classification:

H01L 29/78
H01L 29/66
H01L 27/108
H01L 27/11587
G11C 11/22
G11C 11/4091

Abstract:

An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

US Patent:

20190279984, Sep 12, 2019

Filed:

May 21, 2019

Appl. No.:

16/418150

Inventors:

- Boise ID, US
Michael Amiel Shore - Boise ID, US
Charles L. Ingalls - Meridian ID, US
Steve V. Cole - Boise ID, US

International Classification:

H01L 27/108
G11C 11/4097
H01L 49/02
G11C 11/4094
G11C 5/02
H01L 29/08
G11C 11/408
G11C 11/403

Abstract:

Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

US Patent:

20190006365, Jan 3, 2019

Filed:

May 22, 2018

Appl. No.:

15/986628

Inventors:

- Boise ID, US
Michael Amiel Shore - Boise ID, US
Charles L. Ingalls - Meridian ID, US
Steve V. Cole - Boise ID, US

Assignee:

Micron Technology , Inc. - Boise ID

International Classification:

H01L 27/108
G11C 11/408
G11C 11/4094
G11C 11/4097
H01L 29/08
H01L 49/02

Abstract:

Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.