Steve J Maxwell

US Patent:

20150318333, Nov 5, 2015

Filed:

Mar 3, 2015

Appl. No.:

14/636363

Inventors:

- Santa Clara CA, US
Steve Maxwell - Sunnyvale CA, US
Natividad Vasquez, JR. - San Francisco CA, US
Harry Yue Gee - Milpitas CA, US

International Classification:

H01L 27/24
H01L 21/768
H01L 23/532
H01L 45/00
H01L 23/522

Abstract:

Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

US Patent:

20150243886, Aug 27, 2015

Filed:

Dec 31, 2014

Appl. No.:

14/587711

Inventors:

- Santa Clara CA, US
Steve Maxwell - Sunnyvale CA, US
Natividad Vasquez, JR. - San Francisco CA, US
Harry Yue Gee - Santa Clara CA, US

International Classification:

H01L 45/00
H01L 27/24

Abstract:

Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

US Patent:

20150228893, Aug 13, 2015

Filed:

Feb 4, 2015

Appl. No.:

14/613585

Inventors:

- Santa Clara CA, US
Steve Maxwell - Sunnyvale CA, US
Natividad Vasquez, JR. - San Francisco CA, US
Harry Yue Gee - Santa Clara CA, US

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.