Steve Kent Porter

US Patent:

6496421, Dec 17, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/653539

Inventors:

Scott Van De Graaff - Boise ID
Steve Porter - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518909, 365149

Abstract:

A voltage reference circuit is provided in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

US Patent:

6700824, Mar 2, 2004

Filed:

Oct 30, 2002

Appl. No.:

10/283308

Inventors:

Scott Van De Graaff - Boise ID
Steve Porter - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518909, 36518908, 36523006

Abstract:

A voltage reference circuit is provided in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

US Patent:

7366045, Apr 29, 2008

Filed:

Dec 22, 2006

Appl. No.:

11/643689

Inventors:

Trevor Hardy - Wichita KS, US
Steve Porter - Boise ID, US
Ethan Williford - Boise ID, US
Mark Ingram - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365205, 365203

Abstract:

A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

US Patent:

7551509, Jun 23, 2009

Filed:

Mar 19, 2008

Appl. No.:

12/076519

Inventors:

Trevor Hardy - Wichita KS, US
Steve Porter - Boise ID, US
Ethan Williford - Boise ID, US
Mark Ingram - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 5/14

US Classification:

365226, 365228

Abstract:

A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.

US Patent:

7269079, Sep 11, 2007

Filed:

May 16, 2005

Appl. No.:

11/129315

Inventors:

Trevor Hardy - Wichita KS, US
Steve Porter - Boise ID, US
Ethan Williford - Boise ID, US
Mark Ingram - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 5/14

US Classification:

36518909, 365149

Abstract:

A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary embodiment, one or more voltages used by a reference circuit which are normally supplied by different taps of a power supply are generated by corresponding power circuits. In accordance with a second exemplary embodiment, the power circuits are coupled to the bit lines and replace the reference circuit in a manner to improve sensing margin.