Steven Adler Adler

US Patent:

53713940, Dec 6, 1994

Filed:

Nov 15, 1993

Appl. No.:

8/153503

Inventors:

Gordon C. Ma - Phoenix AZ
Hassan Pirastehfar - Mesa AZ
Steven J. Adler - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2968
H01L 2104

US Classification:

257335

Abstract:

An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.

US Patent:

52528480, Oct 12, 1993

Filed:

Feb 3, 1992

Appl. No.:

7/829190

Inventors:

Steven J. Adler - Tempe AZ
Robert B. Davies - Tempe AZ
Stephen J. Nugent - Phoenix AZ
Hassan Pirastehfar - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2978
H01L 2910

US Classification:

257328

Abstract:

A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

US Patent:

55567932, Sep 17, 1996

Filed:

Nov 1, 1993

Appl. No.:

8/144623

Inventors:

Steven J. Adler - Tempe AZ
George W. Hawkins - Mesa AZ
Israel A. Lesk - Phoenix AZ
Peter L. Pegler - Mesa AZ
Hassan Pirastehfar - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21322

US Classification:

437 11

Abstract:

A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.