Steven G Baldwin

US Patent:

41410270, Feb 20, 1979

Filed:

May 19, 1978

Appl. No.:

5/907725

Inventors:

Steven M. Baldwin - San Diego CA
Donald L. Henderson - Encinitas CA
Joel A. Karp - Palo Alto CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

H01L 2704
H01L 2978

US Classification:

357 51

Abstract:

An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps. A subsequent source and drain diffusion causes lateral migration of the conductive portions of the cell to increase the storage capacitance and to insure electrical contact between the island region of the capacitor and the source of the transfer transistor.

US Patent:

39978133, Dec 14, 1976

Filed:

Nov 10, 1975

Appl. No.:

5/630218

Inventors:

Stephen J. C. Chan - San Diego CA
Donald L. Henderson - Encinitas CA
Steven M. Baldwin - San Diego CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

H05B 4114

US Classification:

315169TV

Abstract:

An MOS integrated circuit chip for both addressing and driving display devices in display panels. The chip includes low-level logic devices for receiving and manipulating data for energizing a selected number of devices in the display panel. An output driver portion is coupled to the display devices and energizes the devices in response to the data received by the input logic. The output driver portion includes a transistor in which the drain region extends deeper into the substrate than the source region of the transistor, as well as the remainder of the active regions in the integrated circuit chip. Accordingly, the integrated circuit chip can withstand a high breakdown voltage at its driver output, while also providing high density logic devices thereby minimizing discrete components and their associated separate electrical interconnections.

US Patent:

41259335, Nov 21, 1978

Filed:

May 2, 1977

Appl. No.:

5/792578

Inventors:

Steven M. Baldwin - San Diego CA
Donald L. Henderson - Encinitas CA
Joel A. Karp - Palo Alto CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

B01J 1700

US Classification:

29571

Abstract:

An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps. A subsequent source and drain diffusion causes lateral migration of the conductive portions of the cell to increase the storage capacitance and to insure electrical contact between the island region of the capacitor and the source of the transfer transistor.