Steven C Chang

US Patent:

8171307, May 1, 2012

Filed:

May 26, 2006

Appl. No.:

11/420723

Inventors:

Steven Chang - Sunnyvale CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 21/00

US Classification:

713189, 380 28, 380239, 380259, 709213, 709250, 713150, 713165, 713182, 713193, 726 2

Abstract:

The invention provides for rekeying a large cluster of storage security appliances which allows more than two of the storage security appliances to proxy a single storage medium while encrypting the storage medium in a manner that is transparent to any attached server. The invention provides a method for synchronizing encryption of the disk among a large cluster of storage security appliances, while allowing all of the storage security appliances involved to access the storage device being rekeyed in a secure fashion.

US Patent:

20050020282, Jan 27, 2005

Filed:

Jun 23, 2004

Appl. No.:

10/874775

Inventors:

Ashutosh Pande - San Jose CA, US
Steven Chang - San Jose CA, US
Lionel Garin - Palo Alto CA, US
Qiyue Zhang - Cupertino CA, US

International Classification:

H04B007/185

US Classification:

455456100, 455012100

Abstract:

A virtual satellite system server that collects and transmits aiding and assisting data to satellite positioning system enabled device upon an event occurring or upon receipt of a message where the virtual satellite system server may also have a location server that contains location data and determines which virtual satellite system server may respond to another device seeking aiding or assisting information in order for the other device to determine it's position.

US Patent:

20060005438, Jan 12, 2006

Filed:

Jul 7, 2004

Appl. No.:

10/710394

Inventors:

Steven Chang - Walnut CA, US
Sonia Chang - Walnut CA, US

International Classification:

G09F 1/00

US Classification:

040124090

Abstract:

An inexpensive, aesthetically pleasing display assembly () is provided in the form of an upstanding carrier () supporting at least one comestible article () such as a multiple-piece simulated candy bouquet (). The carrier () includes a pair of interconnected, angularly oriented panels (), with the panel () having an uppermost open mouth () and an elongated passageway (). The simulated bouquet () comprises a plurality of candy pieces () each supported by an elongated stem (). The bouquet stems () are inserted into passageway (), and the panels () are separated so as to form a stable, upstanding, self-supporting display assembly ().

US Patent:

20070150699, Jun 28, 2007

Filed:

Dec 28, 2005

Appl. No.:

11/321213

Inventors:

Ioannis Schoinas - Portland OR, US
Doddaballapur Jayasimha - Sunnyvale CA, US
Eric Delano - Fort Collins CO, US
Allen Baum - Palo Alto CA, US
Akhilesh Kumar - Sunnyvale CA, US
Steven Chang - Portland OR, US
Suresh Chittor - Portland OR, US
Kenneth Creta - Gig Harbor WA, US
Stephen Van Doren - Portland OR, US

International Classification:

G06F 15/00

US Classification:

712013000

Abstract:

Methods and apparatuses for firm partitioning of a computing platform.

US Patent:

20130268747, Oct 10, 2013

Filed:

Dec 29, 2011

Appl. No.:

13/993614

Inventors:

Steven S. Chang - San Jose CA, US
Anshuman Thakar - Beaverton OR, US
Ramacharan Charan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US

International Classification:

G06F 1/24

US Classification:

713 2

Abstract:

An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.

US Patent:

20130339663, Dec 19, 2013

Filed:

Dec 29, 2011

Appl. No.:

13/993663

Inventors:

Steven S. Chang - San Jose CA, US
Anshuman Thakar - Beaverton OR, US
Ramacharan Charan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US

International Classification:

G06F 15/80

US Classification:

712 29

Abstract:

This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

US Patent:

20140006763, Jan 2, 2014

Filed:

Dec 29, 2011

Appl. No.:

13/993573

Inventors:

Steven S. Chang - San Jose CA, US
Anshuman Thakur - Beaverton OR, US
Ramacharan Charan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US

International Classification:

G06F 9/44

US Classification:

713 1

Abstract:

This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

US Patent:

20140006767, Jan 2, 2014

Filed:

Dec 29, 2011

Appl. No.:

13/993310

Inventors:

Steven S. Chang - San Jose CA, US
Anshuman Thakur - Beaverton OR, US
Ramacharan Charan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US
Jay S. Lawlor - Hillsboro OR, US
Robert F. Netting - Hillsboro OR, US

International Classification:

G06F 9/44

US Classification:

713 2

Abstract:

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.