Steven Chen

US Patent:

6393046, May 21, 2002

Filed:

Apr 25, 1997

Appl. No.:

08/846067

Inventors:

Sanjai Kohli - Manhattan Beach CA
Steven Chen - Cerritos CA
Charles R. Cahn - Manhattan Beach CA
Mangesh Chansarkar - Santa Clara CA
Greg Turetsky - San Jose CA

Assignee:

SiRF Technology, Inc. - San Jose CA

International Classification:

H04L 2330

US Classification:

375134, 375130, 375137, 375140, 375142

Abstract:

A terrestrial C/A code GPS receiver system digitally samples, filters and stores a segment of 11 half chips of the received composite as a binary number and multiplexes this number for parallel correlation with each of a series of multibit code replicas for the satellites to be tracked. Each of the time delay specific correlation products are accumulated in a cell of a memory matrix so that at least twenty two delays for each satellite may be evaluated each code period providing fast reacquisition, even within a city intersection, as well as correction of multipath tracking and multipath interference. All cells of the memory matrix may be used for a acquisition of a single satellite in about 4 ms. Two satellite tracking, in addition to altitude hold, uses cross track hold alternating with clock hold to update the cross track estimate. Single satellite tracking uses cross track and clock hold together.

US Patent:

6400753, Jun 4, 2002

Filed:

Sep 5, 2000

Appl. No.:

09/655633

Inventors:

Sanjai Kohli - Manhattan Beach CA
Steven Chen - Cerritos CA
Charles R. Cahn - Manhattan Beach CA
Mangesh Chansarkar - Santa Clara CA
Greg Turetsky - San Jose CA

Assignee:

SiRF Technology, Inc. - San Jose CA

International Classification:

H04L 2730

US Classification:

375134, 375130, 375137, 375140, 375142

Abstract:

A terrestrial C/A code GPS receiver system digitally samples, filters and stores a segment of 11 half chips of the received composite as a binary number and multiplexes this number for parallel correlation with each of a series of multibit code replicas for the satellites to be tracked. Each of the time delay specific correlation products are accumulated in a cell of a memory matrix so that at least twenty two delays for each satellite may be evaluated each code period providing fast reacquisition, even within a city intersection, as well as correction of multipath tracking and multipath interference. All cells of the memory matrix may be used for a acquisition of a single satellite in about 4 ms. Two satellite tracking, in addition to altitude hold, uses cross track hold alternating with clock hold to update the cross track estimate. Single satellite tracking uses cross track and clock hold together.

US Patent:

6423949, Jul 23, 2002

Filed:

May 19, 1999

Appl. No.:

09/314845

Inventors:

Steven Aihua Chen - Fremont CA
Henry Ho - San Jose CA
Michael X. Yang - Fremont CA
Bruce W. Peuse - San Carlos CA
Karl Littau - Palo Alto CA
Yu Chang - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H05B 368

US Classification:

2194441, 118725

Abstract:

A heating apparatus including a stage comprising a surface having an area to support a wafer and a body, a shaft coupled to the stage, and a first and a second heating element. The first heating element is disposed within a first plane of the body of the stage. The second heating element is disposed within a second plane of the body of the stage at a greater distance from the surface of the stage than the first heating element. A reactor comprising a chamber, a resistive heater, a first temperature sensor, and a second temperature sensor. A resistive heating system for a chemical vapor deposition apparatus comprising a resistive heater. A method of controlling the temperature in a reactor comprising providing a resistive heater in a chamber of a reactor, measuring the temperature with at least two temperature sensors, and controlling the temperature in the reactor by regulating a power supply to the first heating element and the second heating element according to the temperature measured by the first temperature sensor and the second temperature sensor.

US Patent:

6566183, May 20, 2003

Filed:

Dec 12, 2001

Appl. No.:

10/017192

Inventors:

Steven A. Chen - San Jose CA 95121
Lee Luo - Fremont CA 94539
Kegang Huang - Fremont CA 94539
Tzy-Tzan Fu - Hsin-Chu 300, TW
Kuan-Ting Lin - Keelung, TW
Hung-Chuan Chen - Hsin-Chu 300, TW

International Classification:

H01L 218238

US Classification:

438230, 438595, 438791

Abstract:

The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

US Patent:

6522682, Feb 18, 2003

Filed:

Mar 2, 1999

Appl. No.:

09/260440

Inventors:

Sanjai Kohli - Manhattan Beach CA
Steven Chen - Cerritos CA

Assignee:

SiRF Technology, Inc. - San Jose CA

International Classification:

H04B 169

US Classification:

375142, 375150, 34235708, 701213

Abstract:

A spread spectrum receiver processes signals from a plurality of sources modulated by different spread spectrum codes by sampling the signals as received to produce an integer series of sampling segments at a sampling rate at least twice a chip rate of the codes, each sampling segment containing an integer number of bits representing a fraction of a chip of the codes, time division multiplexing each sample segment into a number of channels, correlating the bits in each sample segment in each channel in parallel with a source specific series of locally generated sequential code samples differing by one bit, summing each parallel correlation, and accumulating the summed parallel correlations for each code sample in each channel at at least the chip rate to derive data related to each of the sources.

US Patent:

6525926, Feb 25, 2003

Filed:

Jul 11, 2000

Appl. No.:

09/613384

Inventors:

Steven Chen - Fremont CA

Assignee:

Racklogic Technologies, Inc. - Fremont CA

International Classification:

H05K 502

US Classification:

361683, 361686, 361725, 361731, 3122232

Abstract:

A modular multinode computing apparatus includes a rack mountable enclosure and more than one system board that is secured within the enclosure in a high density configuration that is preferably configured so that the system boards are positioned in substantially the same plane, which is also the plane in which the apparatus resides when mounted within a rack. The enclosure preferably has four system boards, and is sized as a 1 u form factor. When mounted in a rack with like units, the apparatus permits a data center or computing cluster to be fabricated that has a processing density that is much greater than conventional clusters that are configured with 1 u based single node units.

US Patent:

6530992, Mar 11, 2003

Filed:

Jul 9, 1999

Appl. No.:

09/350632

Inventors:

Michael X. Yang - Fremont CA
Henry Ho - San Jose CA
Steven A. Chen - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1600

US Classification:

118695, 118697, 118704, 118715, 118725, 118728, 438791, 700121

Abstract:

Methods and apparatuses of forming a film on a substrate including introducing a pretreatment material into a processing chamber sufficient to form a film as a portion of an inner surface of the processing chamber to inhibit outgassing from that portion of the chamber, introducing a substrate into the chamber, and forming a film on the substrate.

US Patent:

6559039, May 6, 2003

Filed:

May 15, 2001

Appl. No.:

09/858821

Inventors:

Shulin Wang - Campbell CA
Lee Luo - Fremont CA
Steven A. Chen - San Jose CA
Errol Sanchez - Dublin CA
Xianzhi Tao - San Jose CA
Zoran Dragojlovic - San Jose CA
Li Fu - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2124

US Classification:

438542, 438541

Abstract:

A method for depositing doped polycrystalline or amorphous silicon film. The method includes placing a substrate onto a susceptor. The susceptor includes a body having a resistive heater therein and a thermocouple in physical contact with the resistive heater. The susceptor is located in the process chamber such that the process chamber has a top portion above the susceptor and a bottom portion below the susceptor. The method further includes heating the susceptor. The method further includes providing a process gas mix into the process chamber through a shower head located on the susceptor. The process gas mix includes a silicon source gas, a dopant gas, and a carrier gas. The carrier gas includes nitrogen. The method further includes forming the doped silicon film from the silicon source gas.