Steven D Clements

US Patent:

8139700, Mar 20, 2012

Filed:

Jun 26, 2009

Appl. No.:

12/492419

Inventors:

Troy J. Beukema - Yorktown Heights NY, US
Steven M. Clements - Research Triangle Park NC, US
Chun-Ming Hsu - Hopewell Junction NY, US
William R. Kelly - Hopewell Junction NY, US
Elizabeth M. May - Research Triangle Park NC, US
Sergey V. Rylov - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 25/00

US Classification:

375371, 375376, 327147, 327153

Abstract:

A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

US Patent:

20130214865, Aug 22, 2013

Filed:

Feb 17, 2012

Appl. No.:

13/399054

Inventors:

John F. Bulzacchelli - Yonkers NY, US
Steven M. Clements - Raleigh NC, US
Sergey V. Rylov - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 3/45

US Classification:

330261

Abstract:

Capacitive level-shifting circuits and methods are provided for adding DC offsets to the output of a current-integrating amplifier. For example, a current-integrating amplifier includes an input amplifier stage and an output offset circuit. The input amplifier stage includes an input node, a first output node, and a first switch connected between the first output node and a power supply node. The output offset circuit is connected to the first output node of the input amplifier stage and to a second output node of the current-integrating amplifier. The output offset circuit includes a first series capacitor coupled between the first output node of the input amplifier stage and the second output node of the current-integrating amplifier. The output offset circuit switchably connects a bias voltage to the second output node and charges the first series capacitor to add a DC offset to the second output node of the current-integrating amplifier.

US Patent:

55180450, May 21, 1996

Filed:

Nov 14, 1994

Appl. No.:

8/339148

Inventors:

Steven D. Clements - Nanuet NY
Thomas O. Jacobsen - Midland Park NJ

Assignee:

Ben Clements & Sons, Inc. - South Hackensack NJ

International Classification:

B21F 1504

US Classification:

140119

Abstract:

A twist tie device for twisting together the ends of the tie ribbon and encircling an article which is positioned therein for tying is provided. The device includes a feed element for feeding the tie ribbon in the device to the article. An arm is provided for guilding the tie ribbon around the article. A twist head, connected to a rod, is provided for tightening the tie ribbon around the article. A gear assembly is provided for rotating and driving the twist head and for driving tie ribbon feed element. A cylinder with a rod plunger, forming an actuator, is coupled to the gear assembly. In response to a control signal, the actuator moves in a first direction between a start position, a first position and a second position. When the actuator moves from a start position to a first position, it makes contact with the arm so that the arm partially wraps the tie ribbon around the article. The actuator then moves to a second position and drives the gear assembly so that the twist head tightens the tie ribbon around the article.