Steven Clements

US Patent:

7863958, Jan 4, 2011

Filed:

Dec 31, 2008

Appl. No.:

12/347469

Inventors:

David William Boerstler - Round Rock TX, US
Steven Mark Clements - Raleigh NC, US
Jieming Qi - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/017

US Classification:

327175

Abstract:

A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.