Steven Mark Clements

US Patent:

7187206, Mar 6, 2007

Filed:

Oct 30, 2003

Appl. No.:

10/697514

Inventors:

Steven M. Clements - Durham NC, US
Carrie E. Cox - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/0175
H03H 11/26

US Classification:

326 82, 326 29, 326 83, 326 86, 326 87, 327 52, 327 65, 327156, 327262

Abstract:

Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.

US Patent:

7307447, Dec 11, 2007

Filed:

Oct 27, 2005

Appl. No.:

11/263138

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Todd M. Rasmus - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H03B 1/00

US Classification:

326 30, 326 27, 327108, 327112

Abstract:

A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.

US Patent:

7368902, May 6, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/262101

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 35/00
H03K 19/003
G06F 19/00

US Classification:

3241581, 324601, 326 30, 363 95, 702107

Abstract:

Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

US Patent:

7411422, Aug 12, 2008

Filed:

Apr 12, 2005

Appl. No.:

11/103789

Inventors:

Steven M. Clements - Raleigh NC, US
Carrie E. Cox - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 86, 326 30, 326 26

Abstract:

A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.

US Patent:

7460602, Dec 2, 2008

Filed:

Apr 29, 2005

Appl. No.:

11/119505

Inventors:

Steven M. Clements - Raleigh NC, US
Carrie E. Cox - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 3/00

US Classification:

375257, 375219, 375229, 375220, 375295, 375316, 398135, 398137, 398195

Abstract:

A high speed serial link method is provided, using a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.

US Patent:

7570071, Aug 4, 2009

Filed:

Feb 8, 2008

Appl. No.:

12/028451

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G01R 35/00
H03K 19/003
G06F 19/00

US Classification:

324765, 324601, 326 30, 702107

Abstract:

Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

US Patent:

7698802, Apr 20, 2010

Filed:

Feb 8, 2008

Appl. No.:

12/028439

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

29593, 29832, 29842, 29846, 29854, 3241581, 324601, 326 30, 363 95, 702107

Abstract:

A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.

US Patent:

7705640, Apr 27, 2010

Filed:

Jan 25, 2008

Appl. No.:

12/019748

Inventors:

Steven M. Clements - Raleigh NC, US
Todd M. Rasmus - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03L 7/06

US Classification:

327157, 327147, 327156, 327158

Abstract:

A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion.