Steven J Decker

US Patent:

6433632, Aug 13, 2002

Filed:

May 26, 2000

Appl. No.:

09/579748

Inventors:

Katsufumi Nakamura - Boston MA
Steven Decker - Derry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 114

US Classification:

330 9, 327124

Abstract:

A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.

US Patent:

6512546, Jan 28, 2003

Filed:

Jul 17, 1998

Appl. No.:

09/118526

Inventors:

Steven Decker - Derry NH
Stuart Boyd - South Hamilton MA
Laurier St. Onge - Londonderry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5335

US Classification:

348308, 348280

Abstract:

In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.

US Patent:

6570615, May 27, 2003

Filed:

Jul 14, 1998

Appl. No.:

09/115011

Inventors:

Steven Decker - Derry NH
Stuart Boyd - South Hamilton MA
Laurier St. Onge - Londonderry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 9083

US Classification:

348272, 348275, 348324, 2502081

Abstract:

In one embodiment, an image sensor includes a linear pixel array and array readout lines, wherein the linear pixel array includes a group of pixels arranged in a row, and each array readout line is selectively coupled to an output of at least one pixel included in the group of pixels. In another embodiment, an image sensor includes a linear pixel array and an array readout line, wherein the linear pixel array includes a first group of pixels, sensitive to a first color of light, arranged in a first row, and a second group of pixels, sensitive to a second color of light, arranged in a second row, and the array readout line is selectively coupled to outputs of pixels included in the first group of pixels and outputs of pixels included in the second group of pixels. In another embodiment, an image sensor includes array readout lines and a pixel, wherein an output of the pixel is selectively coupled to each of the array readout lines such that the contents of the pixel may be provided to any one of the array readout lines without being provided to any other of the array readout lines. In another embodiment, an image sensor includes a linear pixel array and array readout lines, wherein the pixel array includes a group of pixels, sensitive to a particular color of light, arranged in a row, and each array readout line is selectively coupled to an output of at least one pixel included in the group of pixels.

US Patent:

6577183, Jun 10, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/882513

Inventors:

Katsufumi Nakamura - Boston MA
Steven Decker - Derry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 102

US Classification:

330 9, 327307

Abstract:

An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.

US Patent:

6864820, Mar 8, 2005

Filed:

Feb 28, 2003

Appl. No.:

10/376515

Inventors:

Katsufumi Nakamura - Andover MA, US
Steven Decker - Derry NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M001/12

US Classification:

341155, 341161

Abstract:

One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.

US Patent:

6965332, Nov 15, 2005

Filed:

Feb 28, 2003

Appl. No.:

10/376467

Inventors:

Katsufumi Nakamura - Andover MA, US
Steven Decker - Derry NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M001/06
H03M001/10

US Classification:

341118, 341120

Abstract:

One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

US Patent:

7123301, Oct 17, 2006

Filed:

May 26, 2000

Appl. No.:

09/579646

Inventors:

Katsu Nakamura - Boston MA, US
Steven Decker - Derry NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5/217
H03F 1/14

US Classification:

348301, 327124, 330 9

Abstract:

A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

US Patent:

7242428, Jul 10, 2007

Filed:

Jun 14, 2002

Appl. No.:

10/172423

Inventors:

Steven Decker - Derry NH, US
Stuart Boyd - South Hamilton MA, US
Laurier St. Onge - Londonderry NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5/335

US Classification:

348272, 348308

Abstract:

In one embodiment, an image sensor includes an area pixel array, column readout lines, and array readout lines, wherein the area pixel array includes columns of pixels, each including pixels of a first type, each column readout line is selectively coupled to outputs of the pixels of the first type that are included in a respective column of pixels, and each array readout line is selectively coupled to at least one of the first column readout lines. In another embodiment, an image sensor includes a pixel array, column readout lines, and array readout lines, wherein the pixel array includes a row of pixels which includes pixels of a first type, each column readout line is selectively coupled to an output of a respective pixel of the first type that is included in the row of pixels, and each array readout line is selectively coupled to at least one of the column readout lines.