Steven J Decker

US Patent:

6433632, Aug 13, 2002

Filed:

May 26, 2000

Appl. No.:

09/579748

Inventors:

Katsufumi Nakamura - Boston MA
Steven Decker - Derry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 114

US Classification:

330 9, 327124

Abstract:

A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.

US Patent:

6577183, Jun 10, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/882513

Inventors:

Katsufumi Nakamura - Boston MA
Steven Decker - Derry NH

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 102

US Classification:

330 9, 327307

Abstract:

An offset correction circuit loop with summing nodes, a variable gain transconductance amplifier and capacitor. The input to the loop is sent to a first summing node and then to a separate circuit. The output of the separate circuit is sent to the output of the loop and to the input of a second summing node. The second summing node subtracts the circuit output from a reference voltage and sends the result to the transconductance amplifier which outputs a corrective current which is then integrated onto the capacitor to produce a corrective input offset voltage estimate.

US Patent:

7123301, Oct 17, 2006

Filed:

May 26, 2000

Appl. No.:

09/579646

Inventors:

Katsu Nakamura - Boston MA, US
Steven Decker - Derry NH, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5/217
H03F 1/14

US Classification:

348301, 327124, 330 9

Abstract:

A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

US Patent:

20120236187, Sep 20, 2012

Filed:

Mar 16, 2011

Appl. No.:

13/049790

Inventors:

Edward Guthrie - Boston MA, US
Masatoshi Sase - , US
Steven Decker - Sandown NH, US
Katsu Nakamura - Andover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5/335

US Classification:

348273, 348294, 348E05091

Abstract:

Previously available analog domain decimation techniques are limited to simple equally-weighted averaging of photosite outputs. Decimation of a Bayer pattern image by an even-factor, such as by two or six, using simple equally-weighted averaging of photosite outputs in the analog domain results in effective sampling locations that are unevenly spaced apart. Standard interpolation of the unevenly spaced effective sampling locations generates image artifacts that reduce the quality of the reconstructed image in the smaller format because standard interpolation methods assume that the effective sampling locations are evenly spaced. Implementations of systems, methods and apparatus disclosed herein aim to produce substantially evenly spaced effective sampling locations in the analog domain. More specifically, in some implementations, the unequally-weighted-average even-factor decimation methods disclosed herein produce substantially more evenly spaced effective sampling locations as compared to the equally-weighted-average even-factor decimation processes previously used in the analog domain.

US Patent:

20130015323, Jan 17, 2013

Filed:

Jun 13, 2012

Appl. No.:

13/517524

Inventors:

Mark T. SAYUK - Reading MA, US
Steven J. DECKER - Sandown NH, US

Assignee:

ANALOG DEVICES, INC. - Norwood MA

International Classification:

H01L 27/148

US Classification:

2502081

Abstract:

Embodiments of the present invention employ a charged-based readout circuit in an image sensing system that includes a column readout circuit which may perform sampling on signals received from a pixel array and transfer a corresponding correlated double sample (CDS) signal, a differential channel readout circuit that may receive the corresponding CDS signal and amplify the signal using an output amplifier, and an output buffer which may receive the amplified CDS signal and output a corresponding signal out of the system. The output amplifier may be composed of two output amplifier paths so that ping-ponging is possible.