Steven Roger Frank

US Patent:

55720595, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/477718

Inventors:

William K. Walker - Plano TX
Steven N. Frank - McKinney TX
Charles M. Hanson - Richardson TX
Robert J. S. Kyle - Rowlett TX
Edward G. Meissner - Dallas TX
Robert A. Owen - Rowlett TX
Gail D. Shelton - Mesquite TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27095

US Classification:

257448

Abstract:

A thermal isolation structure (10) is disposed between a focal plane array and an integrated circuit substrate (12). The thermal isolation structure (10) includes a mesa-type formation (16) and a mesa strip conductor (18, 26) extending from the top of the mesa-type formation (16) to an associated contact pad (14) on the integrated circuit substrate (12). After formation of the mesa-type formation (16) and the mesa strip conductor (18, 26), an anisotropic etch using the mesa strip conductor (18, 26) as an etch mask removes excess mesa material to form trimmed mesa-type formation (24) for improved thermal isolation. Bump bonding material (20) may be deposited on mesa strip conductor (18, 26) and can also be used as an etch mask during the anisotropic etch. Thermal isolation structure (100) can include mesa-type formations (102), each with a centrally located via (110) extending vertically to an associated contact pad (104) of integrated circuit substrate (106). A conductor (108) is deposited on top of mesa-type formation (102), along the walls of via (110), and overlaying contact pad (104).

US Patent:

55870902, Dec 24, 1996

Filed:

Apr 4, 1994

Appl. No.:

8/222146

Inventors:

James F. Belcher - Plano TX
Steven N. Frank - McKinney TX
John P. Long - Garland TX
Jeanee Jones - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B44C 122
C03C 1500

US Classification:

216 17

Abstract:

A novel multiple level mask (e. g. tri-level mask 36) process for masking achieves a desired thick mask with substantially vertical walls and thus improves the ion milling process of ceramic materials (e. g. BST). An embodiment of the present invention is a microelectronic structure comprising a ceramic substrate, an ion mill mask layer (e. g. photoresist 42) overlaying the substrate, a dry-etch-selective mask layer (e. g. TiW 40) overlaying the ion mill mask layer, the dry-etch-selective mask layer comprising a different material than the ion mill mask layer, a top photosensitive layer (38) overlaying the dry-etch-selective mask layer, the top photosensitive layer comprising a different material than the dry-etch-selective mask layer, and a predetermined pattern formed in the top photosensitive layer, the dry-etch-selective mask layer and the ion mill mask layer. The predetermined pattern has substantially vertical walls in the ion mill mask layer.

US Patent:

54245443, Jun 13, 1995

Filed:

Apr 29, 1994

Appl. No.:

8/235835

Inventors:

Gail D. Shelton - Mesquite TX
James F. Belcher - Plano TX
Steven N. Frank - McKinney TX
Charles M. Hanson - Richardson TX
Edward G. Meissner - Dallas TX
Robert A. Owen - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 533

US Classification:

250332

Abstract:

A thermal detection system (100, 200) includes a focal plane array (102, 202), a thermal isolation structure (104, 204) and an integrated circuit substrate (106, 206). The focal plane array (102, 202) includes thermal sensors (114, 214) formed from a pyroelectric element (116, 216), such as barium strontium titanate (BST). One side of the pyroelectric element (116, 216) is coupled to a contact pad (110, 210) disposed on the integrated circuit substrate (106, 206) through a mesa strip conductor (112, 212) of the thermal isolation structure (104, 204). The other side of the pyroelectric element (116, 216) is coupled to a common electrode (120, 220). In one embodiment, slots (128) are formed in the common electrode (120) intermediate the thermal sensors (114) to improve inter-pixel thermal isolation. In another embodiment, slots (236) are formed in the optical coating (224) to improve inter-pixel thermal isolation. The common electrode (120, 220) may be formed from a thermally insulating material, such as a silicon monoxide and chromium matrix (cermet) or other metal oxide.

US Patent:

42294908, Oct 21, 1980

Filed:

Sep 1, 1978

Appl. No.:

5/938748

Inventors:

Steven N. Frank - McKinney TX
James G. Frank - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B05D 512

US Classification:

427113

Abstract:

An improved method of making a fuel cell electrode wherein a thin carbonized paper-like substrate is first impregnated with an electrolyte-repelling material, and thereafter a thin layer of catalyst material is screen printed thereupon.

US Patent:

56460660, Jul 8, 1997

Filed:

Mar 1, 1995

Appl. No.:

8/396944

Inventors:

Steven N. Frank - McKinney TX
James F. Belcher - Plano TX
Charles E. Stanford - Plano TX
Robert A. Owen - Rowlett TX
Robert J. S. Kyle - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

437180

Abstract:

This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing a common electrode layer 31 over the thermal isolation trenches 22; depositing an optical coating 26 above the common electrode layer 31; mechanically thinning the substrate to expose the trench filler 24; etching to remove the trench filler 24 in the bias contact area; depositing a contact metal 34 on the backside of the substrate 20, wherein the contact metal 34 connects to the common electrode layer 31 at bias contact areas 34 around a periphery of the thermal isolation trenches; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. Bias contact vias 23 may be formed in the bias contact areas and then filled with bias contact metal 49. Alternately, the bias contact vias may also be filled with the contact metal 34.

US Patent:

56960026, Dec 9, 1997

Filed:

Apr 19, 1996

Appl. No.:

8/635047

Inventors:

Steven N. Frank - McKinney TX
James F. Belcher - Plano TX
Charles E. Stanford - Plano TX
Robert A. Owen - Rowlett TX
Robert J. S. Kyle - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 3118

US Classification:

437 2

Abstract:

This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing a common electrode layer 31 over the thermal isolation trenches 22; depositing an optical coating 26 above the common electrode layer 31; mechanically thinning the substrate to expose the trench filler 24; etching to remove the trench filler 24 in the bias contact area; depositing a contact metal 34 on the backside of the substrate 20, wherein the contact metal 34 connects to the common electrode layer 31 at bias contact areas 34 around a periphery of the thermal isolation trenches; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. Bias contact vias 23 may be formed in the bias contact areas and then filled with bias contact metal 49. Alternately, the bias contact vias may also be filled with the contact metal 34.

US Patent:

55773095, Nov 26, 1996

Filed:

Mar 1, 1995

Appl. No.:

8/397512

Inventors:

Steven N. Frank - McKinney TX
James F. Belcher - Plano TX
Charles E. Stanford - Plano TX
Robert A. Owen - Rowlett TX
Robert J. S. Kyle - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 3118

US Classification:

29 2542

Abstract:

This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 and contact vias 23 in a substrate 20; depositing a bias contact metal 32 into the vias 23 forming biasing contact areas around a periphery of the substrate 20; depositing a first trench filler 24 in the trenches 22 and vias 23; replanarizing; depositing a common electrode layer 25 over the thermal isolation trenches and the biasing contact areas; mechanically thinning the substrate 20 to expose the biasing contact area 32 and the trench filler 24; depositing a contact metal 34 on the backside of the substrate 20, the exposed trench filler 24 and the exposed bias contact area; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. The thermal isolation trenches 22 and the bias contact vias 23 may be formed by ion milling or laser vaporization. Alternately, the bias contact areas 23 may be formed by performing laser vaporization on the substrate 20 to produce conductive 23 areas within the substrate.

US Patent:

55523269, Sep 3, 1996

Filed:

Mar 1, 1995

Appl. No.:

8/397706

Inventors:

Steven N. Frank - McKinney TX
James F. Belcher - Plano TX
Charles E. Stanford - Plano TX
Robert A. Owen - Rowlett TX
Robert J. S. Kyle - Rowlett TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 3118
H01L 2158

US Classification:

437 3

Abstract:

This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches 22 and bias contact vias 23 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing conductive epoxy 50 into the bias contact vias 23; replanarizing; depositing a common electrode layer 31 over the thermal isolation trenches 22 and vias 23; depositing an optical coating 26 above the common electrode layer 31; mechanically polishing a backside of the substrate 20 to expose the trench filler 24 and conductive epoxy 50; depositing a contact metal 34 on the backside of the substrate 20; etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20.