Steven William Frank

US Patent:

47559306, Jul 5, 1988

Filed:

Jun 27, 1985

Appl. No.:

6/749581

Inventors:

Andrew W. Wilson - Pittsburgh PA
Steven J. Frank - Southboro MA

Assignee:

Encore Computer Corporation - Marlboro MA

International Classification:

G06F 1208
G06F 1212

US Classification:

364200

Abstract:

A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.