Steven Lynn Holmes

US Patent:

8137893, Mar 20, 2012

Filed:

Jan 1, 2011

Appl. No.:

12/983297

Inventors:

Sean David Burns - Armonk NY, US
Matthew E. Colburn - Armonk NY, US
Steven John Holmes - Armonk NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 7/00
G03F 7/004
G03F 7/40

US Classification:

4302701, 430311, 430312, 430317, 430318, 430322, 430300, 430331

Abstract:

A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e. g. , about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line.

US Patent:

20090321833, Dec 31, 2009

Filed:

Jun 25, 2008

Appl. No.:

12/145616

Inventors:

Hariklia Deligianni - Tenafly NJ, US
Toshiharu Furukawa - Essex Junction VT, US
Steven J. Holmes - Guilderland NY, US
David V. Horak - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257365, 438283, 257E29264, 257E21421

Abstract:

Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

US Patent:

20130168775, Jul 4, 2013

Filed:

Feb 27, 2013

Appl. No.:

13/778826

Inventors:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY, US
Toshiharu Furukawa - Essex Junction VT, US
Steven J. Holmes - Guilderland NY, US
Sivananda K. Kanakasabapathy - Niskayuna NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/66
H01L 29/78

US Classification:

257368, 438305

Abstract:

A field effect transistor device prepared by a process including forming a first gate stack and a second gate stack on a substrate and depositing a first photoresist material over the second gate stack and a portion of the substrate. The process also includes implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack and depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material. The process further includes removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region and removing the first photoresist material.

US Patent:

20130175658, Jul 11, 2013

Filed:

Mar 5, 2013

Appl. No.:

13/784959

Inventors:

International Business Machines Corporation - Armonk NY, US
Sean D. Burns - Hopewell Junction NY, US
Matthew E. Colburn - Schenectady NY, US
Steven J. Holmes - Guilderland NY, US
Yunpeng Yin - Niskayuna NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 23/00

US Classification:

257499

Abstract:

A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

US Patent:

55166083, May 14, 1996

Filed:

Feb 28, 1994

Appl. No.:

8/203212

Inventors:

Philip C. D. Hobbs - Briarcliff Manor NY
Steven Holmes - Burlington VT
Robert Jackson - Millbrook NY
Jerry C. Shaw - Ridgefield CT
John L. Sturtevant - Essex VT
Theodore G. van Kessel - Millbrook NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03C 500
G01B 902
G01B 1102

US Classification:

430 30

Abstract:

In a photolithographic process utilizing a wafer coated with a chemically amplified photoresist, a method for controlling a line dimension. The method comprises the steps of measuring at at least two times, and from at least two angles, evolving signals comprising intensities of light diffracted from a portion of an exposed patterned area on the waver, the evolving signals corresponding to vector combinations of time dependent light diffracted from the pattern appearing in the photoresist; and substantially time invariant light diffracted due to any underlying pattern beneath the photoresist; and, combining the measurements mathematically for extracting a contribution due to the pattern evolving in the photoresist.

US Patent:

20210257536, Aug 19, 2021

Filed:

Feb 14, 2020

Appl. No.:

16/791436

Inventors:

- ARMONK NY, US
Steven J. Holmes - Ossining NY, US
Ning Li - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01L 39/24
H01L 39/12

Abstract:

According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.

US Patent:

20210135085, May 6, 2021

Filed:

Nov 6, 2019

Appl. No.:

16/675651

Inventors:

- Armonk NY, US
Steven J. Holmes - Ossining NY, US
Ning Li - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01L 39/24
G03F 1/36

Abstract:

A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.

US Patent:

20200348256, Nov 5, 2020

Filed:

May 2, 2019

Appl. No.:

16/402206

Inventors:

- Armonk NY, US
Steven J. Holmes - Ossining NY, US
Bruce B. Doris - Slingerlands NY, US

International Classification:

G01N 27/327
H01L 21/02
H01L 29/06

Abstract:

An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.