Steven J Holmes

US Patent:

6338934, Jan 15, 2002

Filed:

Aug 26, 1999

Appl. No.:

09/383452

Inventors:

Kuang-Jung R. Chen - Poughkeepsie NY
Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
Paul A. Rabidoux - Winooski VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 7004

US Classification:

4302701, 430914, 430919

Abstract:

A photo resist composition contains a polymer resin, a first photo acid generator (PAG) requiring a first dose of actinic energy to generate a first photo acid, and a photo base generator (PBG) requiring a second dose of actinic energy, different from the first dose, to generate a photo base. The amounts and types of components in the photo resist are selected to produce a hybrid resist image. Either the first photo acid or photo base acts as a catalyst for a chemical transformation in the resist to induce a solubility change. The other compound is formulated in material type and loading in the resist such that it acts as a quenching agent. The catalyst is formed at low doses to induce the solubility change and the quenching agent is formed at higher doses to counterbalance the presence of the catalyst. Accordingly, the same frequency doubling effect of conventional hybrid resist compositions may be obtained, however, either a line or a space may be formed at the edge of an aerial image. Feature size may also be influenced by incorporating a quenching agent into the resist composition that does not require photo generation.

US Patent:

6342323, Jan 29, 2002

Filed:

Mar 13, 2000

Appl. No.:

09/523796

Inventors:

William Hsioh-Lien Ma - Fishkill NY
David Vaclay Horak - Essex Junction VT
Toshiharu Furukawa - Essex Junction VT
Steven J. Holmes - Milton VT
Mark Charles Hakey - Milton VT

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G03F 900

US Classification:

430 22, 356399

Abstract:

An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

US Patent:

6614074, Sep 2, 2003

Filed:

Jun 5, 1998

Appl. No.:

09/092749

Inventors:

Gary Bronner - Stormville NY
Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
David Horak - Essex Junction VT
Jack A. Mandelman - Stormville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2976

US Classification:

257330, 257332, 257334

Abstract:

A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

US Patent:

6656807, Dec 2, 2003

Filed:

Jan 30, 2001

Appl. No.:

09/772378

Inventors:

Gary Bronner - Stormville NY
Toshiharu Furukawa - Essex Junction VT
Mark C. Hakey - Milton VT
Steven J. Holmes - Milton VT
David Horak - Essex Junction VT
Jack A. Mandelman - Stormville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438296, 438424, 438430, 438433

Abstract:

A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

US Patent:

6780736, Aug 24, 2004

Filed:

Jun 20, 2003

Appl. No.:

10/604009

Inventors:

Steven J. Holmes - Wappingers Falls NY
Toshiharu Furukawa - Essex Junction VT
Arpan P. Mahorowala - Bronxville NY
Dirk Pfeiffer - Dobbs Ferry NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21425

US Classification:

438514, 438515, 438527

Abstract:

A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

US Patent:

6846727, Jan 25, 2005

Filed:

May 21, 2001

Appl. No.:

09/861590

Inventors:

Keith E. Fogel - Mohegan Lake NY, US
Mark C. Hakey - Fairfax VT, US
Steven J. Holmes - Milton VT, US
Devendra K. Sadana - Pleasantville NY, US
Ghavam G. Shahidi - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120
H01L 21425
H01L 2131

US Classification:

438479, 438480, 438527, 438530, 438766, 257 64, 257 66

Abstract:

Methods for forming a patterned SOI region in a Si-containing substrate are provided which has geometries of about 0. 25 μm or less. The methods disclose each utilize a patterned dielectric mask that includes at least one opening having a size of about 0. 25 μm or less which exposes a portion of a Si-containing substrate. Oxygen ions are implanted through the opening using at least a base ion implantation process which is carried out at an oxygen beam energy of about 120 keV or less and an oxygen dosage of about 4E17 cmor less. These conditions minimize erosion of the vertical edges of the patterned dielectric mask and minimize formation of lateral straggles.

US Patent:

6989323, Jan 24, 2006

Filed:

Apr 28, 2004

Appl. No.:

10/709314

Inventors:

Bruce B. Doris - Brewster NY, US
Toshiharu Furukawa - Essex Junction VT, US
Mark C. Hakey - Fairfax VT, US
Steven J. Holmes - Guilderland NY, US
David V. Horak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205
H01L 21/4763

US Classification:

438596, 438585, 438720

Abstract:

A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

US Patent:

6995065, Feb 7, 2006

Filed:

Dec 10, 2003

Appl. No.:

10/732657

Inventors:

Anthony I. Chou - Beacon NY, US
Toshiharu Furukawa - Essex Junction VT, US
Steven J. Holmes - Guilderland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/8238

US Classification:

438303, 438230, 438231, 438305, 438595

Abstract:

A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.