Steven M Holmes

US Patent:

7102452, Sep 5, 2006

Filed:

Dec 31, 2004

Appl. No.:

11/026750

Inventors:

Steven L. Holmes - Sammamish WA, US

Assignee:

ZiLOG, Inc. - San Jose CA

International Classification:

H03K 3/26

US Classification:

331111, 331143, 331176, 331175

Abstract:

An on-chip oscillator generates a substantially temperature-independent clock signal by compensating for temperature-induced changes in its RC time constant and in a range between trigger voltages. A resistor with a positive temperature coefficient determines the range between trigger voltages, which increases with increasing temperature. A comparator response time is part of a delay period that occurs after a trigger voltage is passed and before the charging or discharging of a capacitor is reversed. After the delay period, a remainder period elapses before the other trigger voltage is passed. As temperature increases, the oscillator increases current supplied to a comparator to decrease the response time. Moreover, as temperature increases, the oscillator increases a charge/discharge current so that the capacitor charges and discharges faster as the range between trigger voltages increases. The delay period and the remainder period are adjusted so that their sum remains substantially constant over a large temperature range.

US Patent:

7148672, Dec 12, 2006

Filed:

Mar 16, 2005

Appl. No.:

11/081292

Inventors:

Steven L. Holmes - Sammamish WA, US

Assignee:

ZiLOG, Inc. - San Jose CA

International Classification:

G05F 3/16
G05F 3/20

US Classification:

323316, 323315, 327539

Abstract:

A bandgap reference circuit (BGRC) that is suitable for low-supply voltage applications outputs an adjustable reference voltage. In an operational mode, main currents flow through diodes and are controlled by a main current generator such that a positive temperature coefficient of a voltage across a resistor compensates for a negative temperature coefficient of a voltage across the diodes. The difference of the voltages across the diodes increases with temperature and is used to generate the main currents having positive temperature coefficients. The BGRC ensures sufficient current flow through the diodes during startup. In a startup mode, a startup current generator outputs startup currents that combine with the main currents and prevent the BGRC from operating at incorrect operating points that would otherwise be stable when insufficient current flows through the diodes. The startup currents are generated when the voltage drop across the resistor is less than a predetermined voltage offset.

US Patent:

20080001850, Jan 3, 2008

Filed:

Jun 6, 2007

Appl. No.:

11/810960

Inventors:

Mark Champion - Kenmore WA, US
Steven Holmes - Sammamish WA, US

International Classification:

G02B 26/10
G09G 5/00

US Classification:

345007000, 359198000

Abstract:

According to embodiments, a beam scanning system such as a scanned beam display or scanned beam image capture system includes a controller having a PLL circuit that is operable to track systematic variations in fast scan frequency, such as those that are a function of slow scan angle. The controller is further operable to modify video clocking to compensate for the systematic variations in fast scan phase as a function of slow scan angle.

US Patent:

62559028, Jul 3, 2001

Filed:

Feb 23, 2000

Appl. No.:

9/511512

Inventors:

Troy N. Gilliland - New Castle WA
Steven L. Holmes - Redmond WA

Assignee:

Zilog, Inc. - Campbell CA

International Classification:

H03F 102

US Classification:

330 9

Abstract:

An amplifier circuit with small die size and low power consumption is described. The design allows a number of switch amplifier circuits to be placed on a single chip. Each of the amplifiers contains a comparator for greater amplification, with a designed-in offset, a small pull-down current, and a diode. The comparators are biased with low current values and the need for large resistors is eliminated. Several such devices can be placed on a chip along with an edge triggered shift register to store the logic levels generated from the switch inputs. The offset, either built-in or externally supplied, sets one comparator input to an offset voltage. The switch is connected to the other input, with the diode and pull-down in parallel between this input and ground or other reference level: When the switch is open, the pull-down takes the input to ground; when the switch is closed, the diode voltage drop holds the input to a voltage above the offset. This arrangement also removes the need for key scanning routines and the pre-changing of switches. The use of relatively high gain comparators reduces the sensitivity of the amplifiers to the properties of the switches and micro-processor output ports with which they are used.