Steven Peter Lindquist

US Patent:

58058621, Sep 8, 1998

Filed:

Nov 16, 1995

Appl. No.:

8/558518

Inventors:

Marlan L. Winter - Austin TX
Kenneth P. Tumin - Austin TX
Steven P. Lindquist - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1560

US Classification:

395500

Abstract:

A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.

US Patent:

57817600, Jul 14, 1998

Filed:

Nov 16, 1995

Appl. No.:

8/558451

Inventors:

Marlan L. Winter - Austin TX
Kenneth P. Tumin - Austin TX
Steven P. Lindquist - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 930

US Classification:

395500

Abstract:

During an electronic circuit simulation, an input file is generated that has source code and stimulus sections. Each of the source code and stimulus sections includes linking portions that each link a portion of the source code to a portion of the stimulus sections. The input file is processed to generate object code and a stimulus file that includes linking portions. The linking portions of the stimulus file allow events to occur that are synchronized with the object code during the running of a simulation program. The linking between the stimulus file and the object code is synchronized because the stimulus file is generated from the input file that has the linking portions. The linking remains synchronized even if the input file is modified. After a simulation, masks (30, 40, 50, 60, 70) can be generated and used to form an integrated circuit (20).

US Patent:

60212713, Feb 1, 2000

Filed:

Jan 15, 1998

Appl. No.:

9/007646

Inventors:

Marlan L. Winter - Austin TX
Kenneth P. Tumin - Austin TX
Steven P. Lindquist - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1900

US Classification:

39550035

Abstract:

A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.

US Patent:

58130411, Sep 22, 1998

Filed:

Jun 6, 1996

Appl. No.:

8/660028

Inventors:

Kenneth L. McIntyre - Dripping Springs TX
Anthony M. Reipold - Austin TX
Daniel W. Pechonis - Austin TX
Steven P. Lindquist - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200
G11C 800

US Classification:

711167

Abstract:

A data processing system (20) having a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match. Continued assertion reduces access time to an external device allowing the user to determine the trade-off between high speed access and low power consumption. Additionally, a speculative burst access is made without regard to match criteria, allowing a device to prepare for access while data processor (22) determines the next device to access. Here a load burst address (LBA) signal is speculatively provided to an activated device, and where the next access is to another device, the speculative access is aborted.